Variable clock cycle for processor, bus and components for...

Details Variable clock cycle for processor, bus and components for... Variable clock cycle for processor, bus and components for...

2000-10-24

2004-07-13

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S320000, C713S322000

Reexamination Certificate

active

06763478

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer systems, and more particularly to a portable computer system that changes system clock speed when entering into battery power mode or entering alternating current mode.
2. Description of the Related Art
In the field of electronic computing, portable computers have attained widespread use. Their small size and transportability make them an invaluable tool to today's on the go individual. Faster CPUs with denser circuits are continually introduced into portable computers providing greater computing ability. These new CPUs, however, require greater energy resources from portable computer batteries. Added or enhanced features such as sound, graphics, and data drives such as digital video disks (DVD), further require additional battery power. More sophisticated software applications may also indirectly require a greater battery drain. Portable computer owners can avoid the worry of energy drain by simply plugging their machines into an alternating current (AC) outlet, however, this defeats the mobility advantage of a portable computer. In many instances there is no outlet to make use of. An alternate solution is to have a backup battery, but an extra battery takes up space and requires that the user assure that it is always properly charged.
To some degree batteries have also improved. Today's batteries provide a greater charge life than their predecessors. Computing capability, namely CPU speeds, seems to always improve faster than battery technology. There is always the need to increase battery life, to extend the period of time required to recharge a battery, and to ultimately provide greater portable use to a portable computer user.
For certain applications such as word processing or spreadsheet programs, the system does not need to run at full performance, especially when the system is under battery power. For demanding applications, applications such as interactive gaming, full performance may be required regardless of whether the system is using AC or battery power.
To make use of the times when a system does not need to be at full performance and to extend the life of a battery, it has been found that a CPU can be operated at a lower clock speed when operating on direct current (battery). The system then is switched over to “performance” mode using a higher clock speed when the computer is operated on AC. Such an approach has been implemented by the Intel® Corporation in its Speedstep™ technology.
When working on battery, a portable PC with Speedstep™ technology automatically detects the change and drops both the CPU clock frequency and voltage. A CPU with Speedstep™ technology can be switched between two performance modes—maximum performance and battery-optimized performance—either automatically or by user command. By default, a portable PC with Speedstep™ technology detects when it is plugged into or unplugged from an AC outlet. When the portable PC is unplugged, the CPU core clock frequency drops to 500 MHz from the peak frequency of 600 MHz or 650 MHz. At the same time, the operating voltage of the CPU drops to 1.35 volts from 1.6 volts. When the portable PC is plugged back into an outlet, the CPU goes back up to peak frequency and increases voltage to 1.6 volts.
Users can also manually adjust the Speedstep™ technology mode operation by accessing an applet, the applet typically appearing as an icon on a Microsoft® Windows® taskbar. For example if the user wants increased performance, although the system is running on battery and low performance mode, the user can go to high performance by initiating the applet and forcing the CPU to go to high performance mode.
It has been found that Speedstep™ technology can reduce the active power of the CPU up to 45% while maintaining up to 80% of the maximum performance. Switching voltage levels provides significant power savings, because power consumption occurs in proportion to the square of voltage. In addition reduction in clock frequency also reduces power consumption. Clock frequency has a linear relationship with power consumption. The reduction in power consumption by reducing the clock frequency is not as dramatic as a reduction in voltage, but there is still considerable power savings.
Now referring to
FIG. 1
, which depicts the prior art Speedstep™ technology. A Speedstep™ transition request may be initiated by a device or application and routed through the Super I/O Controller. The computer's Operating System (OS) is made aware of such a request and the transition request is made. The OS recognizes that the PC's power source is being switched from battery to AC, or from AC to battery. The request may also be due to initiating the Speedstep™ applet.
As the Speedstep™ transition request is made, the OS conducts normal system or house keeping processes, then the OS transfers control to a Speedstep™ driver. The Super I/O Controller
10
passes Speedstep™ driver transition protocols by a bus to a South Bridge application specific integrated circuit (ASIC) controller
20
. The Speedstep™ driver transition protocols are coordinated between the South Bridge ASIC
20
and an Intel ® (Geyserville ™ ASIC
40
through an interface
22
.
The Speedstep™ driver then commands the South Bridge ASIC
20
to put the Speedstep™ CPU
70
into a deep sleep, also known as a C
3
, state. The C
3
state is one of four power states, the other three being C
0
, C
1
, and C
2
, defined by the Advance Configuration and Power Interface (ACPI) Specification. The ACPI Specification has been adopted by various CPU manufacturers and other parties in the computing industry. The ACPI Specification power states, in particular, addresses the condition(s) that a CPU is in while in a specific state, in particular power consumption and thermal management conditions. While in the C
3
state, the CPU's caches maintain state but ignore any snoops (inquiries). The operating software is responsible for ensuring that the caches maintain coherency. It has been found that while the Speedstep™ CPU
70
is in C
3
state, frequency transition and voltage transition can be optimally changed. Duties of the Speedstep™ CPU
70
are greatly reduced while in the C
3
state. For example while in the C
3
state, other chipset hardware will maintain CPU cache coherency since the Speedstep™ CPU
70
while in C
3
is unable to support this function.
During C
3
state, the SDRAM Memory
90
enters a self refresh mode to maintain content. The SDRAM Memory
90
is connected by memory bus
95
to the North Bridge ASIC
30
. A memory clock signal
80
is sent to the SDRAM Memory
90
from the Memory Clock Buffer
80
. While in C
3
state, the memory clock signal
80
is stopped, along with any other clocks that may go to the Speedstep™ CPU
70
and the North Bridge ASIC
30
.
Once the Speedstep™ CPU
70
is in C
3
state, the Geyserville™ ASIC
40
provides a voltage hi/lo instruction
55
to the CPU Power Supply
60
. The CPU Core Voltage
110
supplied by CPU Power Supply
60
is then adjusted according to the performance mode of the Speedstep™ transition, a higher voltage for high performance and a lower voltage for low performance.
In addition, while the Speedstep™ CPU
70
is in C
3
state, Geyserville™ ASIC
40
notifies the North Bridge ASIC
30
and the Speedstep™ CPU
70
that the performance mode will change. The Geyserville™ ASIC
40
interfaces with the North Bridge ASIC
30
through South Bridge ASIC
20
. South Bridge ASIC
20
in turn communicates to North Bridge ASIC
30
by peripheral component interconnect (PCI) Bus
25
. South Bridge ASIC
20
primarily controls PCI Devices, such as PCI Device
110
and PCI Device
120
along the PCI Bus
25
. The PCI bus will always run at a clock frequency of 33 MHz. The 33 MHz clock frequency is inherent to the PCI bus.
Control information is passed by South Bridge ASIC
20
to the North Bridge ASIC
30
, the North Bridge ASIC
30
in turn passes the information to the Speedstep™ CPU
70
by the Front Side Bus (

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