Variable clock configuration for switched op-amp circuits

Details Variable clock configuration for switched op-amp circuits Variable clock configuration for switched op-amp circuits

2007-04-10

2007-04-10

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S501000

Reexamination Certificate

active

09932891

ABSTRACT:
A clock configuration for driving switched op-amp circuits operated in opposite phases is presented in which a common off-phase of variable length is inserted between the on-phases of the individual operational amplifiers. The length of the off-phase can be adapted to the transient response of the operational amplifiers used. The clock configuration according to the invention can be used for further reducing the power consumption of switched op-amp circuits.

REFERENCES:
patent: 4551638 (1985-11-01), Varadarajan
patent: 4951303 (1990-08-01), Larson
patent: 5097208 (1992-03-01), Chiang
patent: 5534863 (1996-07-01), Everitt et al.
patent: 5598326 (1997-01-01), Liu et al.
patent: 5723998 (1998-03-01), Saito et al.
patent: 5745002 (1998-04-01), Baschirotto et al.
patent: 5796360 (1998-08-01), Wendelrup
patent: 5818276 (1998-10-01), Garrity et al.
patent: 5880619 (1999-03-01), Barrett, Jr. et al.
patent: 5994960 (1999-11-01), Baschirotto et al.
patent: 6037836 (2000-03-01), Yoshizawa
patent: 6081218 (2000-06-01), Ju et al.
patent: 6232845 (2001-05-01), Kingsley et al.
patent: 6310953 (2001-10-01), Yoshida et al.
patent: 6344767 (2002-02-01), Cheung et al.
patent: 6392466 (2002-05-01), Fletcher
patent: 6477115 (2002-11-01), Inoshita et al.
patent: 6617908 (2003-09-01), Thomsen et al.
patent: 6646396 (2003-11-01), Brown et al.
patent: 6653967 (2003-11-01), Hamashita
patent: 0 689 268 (1995-12-01), None
patent: 0 836 275 (1998-04-01), None
patent: 60-74815 (1985-04-01), None
patent: WO 96/25795 (1996-08-01), None
A. Baschirotto et al.: “A 1V CMOS fully differential switched-opamp bandpass Σ Δ modulator”, Solid State Circ. Conf. 1997 (ESSCIRC 97), pp. 152-155.
M. Steyaert et al.: “Switched-Opamp, a Technique for Realising full CMOS Switched-Capacitor Filters at Very Low Voltages”, Solid State Circ. Conf. 1993 (ESSCIRC 93), pp. 178-181.

Affiliated with

Also associated with

Rating

Variable clock configuration for switched op-amp circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Variable clock configuration for switched op-amp circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Variable clock configuration for switched op-amp circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3757384