Variable and tunable V.sub.T MOSFET with poly and/or buried diff

Details Variable and tunable V.sub.T MOSFET with poly and/or buried diff Variable and tunable V.sub.T MOSFET with poly and/or buried diff

1997-05-15

1998-09-29

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257320, 257314, 257316, H01L 2976

Patent

active

058148566

ABSTRACT:
A MOSFET structure that utilizes self-aligned polysilicon and/or buried diffusion lines for coupling capacitors, provides a threshold voltage V.sub.T that is tunable from the control gate from positive (enhancement) to negative (depletion) by applying V.sub.cc to the bias gate and carefully designing the coupling ratio of the control gate and the bias gate. This scheme provides multiple V.sub.T 's on-chip without process complexity.

REFERENCES:
patent: 4713677 (1987-12-01), Tigelaar et al.
patent: 5530275 (1996-06-01), Widdershoven
Shibata, Tadashi et al., "A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations", IEEE Transactions on Electron Devices, vol. 39, No. 6, pp. 1444-1455, Jun. 1992.

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