Validating partial reconfiguration of an integrated circuit

Details Validating partial reconfiguration of an integrated circuit Validating partial reconfiguration of an integrated circuit

2007-10-09

2009-06-02

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000

Reexamination Certificate

active

07541833

ABSTRACT:
Approaches for validating a configuration bitstream used for partially reconfiguring an ingrated circuit such as a programmable logic device (PLD) are disclosed. In one approach, the integrated circuit is configured with a first configuration bitstream that includes first bit values that produce an implementation of a static part of a design on the integrated circuit. Any differences between a bit value in a second configuration bitstream and a corresponding bit value of the implementation of the static part of the design are determined. The second configuration bitstream includes second bit values that produce an implementation of a reconfigurable part of the design on the integrated circuit. A first signal state is output in response to determining that there are no differences, and a second signal state is output in response to determining that there are differences.

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U.S. Appl. No. 10/917,033, Patterson, Cameron D. et al., entitled “Method and System for Identifying Essential Configuration Bits”, filed Aug. 12, 2004 (52 pages), Xilinx, Inc., 2100 Logic Drive, San Jose, California.
U.S. Appl. No. 10/917,064, Patterson, Cameron D. et al., entitled “Method and System for Generating a Bitstream View of a Design” filed Aug. 12, 2004 (51 pages), Xilinx, Inc., 2100 Logic Drive, San Jose, California.

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