Validating data using processor instructions

Details Validating data using processor instructions Validating data using processor instructions

2011-04-12

2011-04-12

Alphonse, Fritz (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S763000, C714S770000

Reexamination Certificate

active

07925957

ABSTRACT:
In one embodiment, the present invention includes a method for determining from a data block in a buffer a number of first operands in a first portion of the buffer and a number of second operands in a second portion of the buffer. Based on these numbers, a cyclic redundancy checksum (CRC) operation may be iteratively performed on the first and second operands to obtain a checksum result. The first and second operands are of a different length, and the checksum operation may be executed using processor instructions corresponding to the different lengths. Other embodiments are described and claimed.

REFERENCES:
patent: 5109498 (1992-04-01), Kamiya et al.
patent: 5323403 (1994-06-01), Elliott
patent: 5663952 (1997-09-01), Gentry, Jr.
patent: 5701316 (1997-12-01), Alferness et al.
patent: 5946467 (1999-08-01), Pathakis et al.
patent: 5974574 (1999-10-01), Lennie et al.
patent: 6029186 (2000-02-01), DesJardins et al.
patent: 6191614 (2001-02-01), Schultz et al.
patent: 6237074 (2001-05-01), Phillips et al.
patent: 6279140 (2001-08-01), Slane
patent: 6631488 (2003-10-01), Stambaugh et al.
patent: 6907466 (2005-06-01), Alexander et al.
patent: 6957321 (2005-10-01), Sheaffer
patent: 6964008 (2005-11-01), Van Meter, III
patent: 7272586 (2007-11-01), Dewan
patent: 7360142 (2008-04-01), Barash
patent: 7421637 (2008-09-01), Martinez et al.
patent: 7594124 (2009-09-01), Durham et al.
patent: 2004/0037319 (2004-02-01), Pandya
patent: 2004/0113814 (2004-06-01), Lochner
patent: 2004/0158793 (2004-08-01), Blightman et al.
patent: 2004/0243729 (2004-12-01), Milliken
patent: 2006/0242532 (2006-10-01), Joglekar et al.
patent: 0 609 595 (1994-08-01), None
patent: 200414042 (2004-08-01), None
patent: 200414045 (2004-08-01), None
patent: I224729 (2004-09-01), None
patent: I238945 (2005-09-01), None
Intel Corporation, “Metro Ethernet: End-To-End Single Vendor Connectivity,” Apr. 7, 2005, pp. 1-9.
U.S. Appl. No. 11/233,742, filed Sep. 23, 2005, entitled “Techniques To Determine Integrity of Information,” by Ronald L. Dammann, et al.
U.S. Appl. No. 11/230,720, filed Sep. 19, 2005, entitled “Techniques to Perform Prefetching of Content in Connection With Integrity Validation Value Determination” by Steven R. King and Frank L. Berry.
U.S. Appl. No. 11/115,656, filed Apr. 26, 2005, entitled “Techniques to Provide Information Validation and Transfer” by Abhijeet Joglekar; Frank L. Berry.
U.S. Appl. No. 11/316,772, filed Dec. 23, 2005, entitled “Performing a Cyclic Redundancy Checksum Operation Responsive to a User-Level Instruction” by Steven R. King, et al.
“The iSCSI CRC23C Digest and the Simultaneous Multiply and Divide Algorithm”. Tuikov, Luben and Vicente Cavanna. Jan. 30, 2002.
“Accelerating High-Speed Networking with Intel® I/O Acceleration Technology”. Intel® I/O Acceleration Technology White Paper. May 2005.
“A Painless Guide to CRC Error Detection Algorithms”. Ross N. Williams. Aug. 19, 2003. http://www.ros.net/crc/download/crc—v3.txt.
“Intel® IOP332 I/O Processor with Intel XScale® Microarchitecture” http://www.intel.com/design/iio/iop332.htm. Date Unknown.
“Intel® IQ80332 Software Development and Processor Evaluation Kit”. http://www.intel.com/design/iio/devkits/iq80332.htm. Date Unknown.
Keith Lauritzen, et. al., Technology@Intel Magazine, “Intel I/O Acceleration Technology Improves Network Performance, Reliabiltiy and Efficiently,” Mar. 2005, pp. 1-11.
Emily R. Blem et al.,Instruction Set Extensions for Cyclic Redundancy Check on a Multithreaded Processor, 7thWorkshop on Media and Stream Processors, Dec. 12, 2005, Barcelona, Spain.
State Intellectual Property Office, P.R. China, First Office Action dated Apr. 7, 2010, in Chinese patent application No. 2007800009844.0.
European Patent Office, Combined Search Report and Search Opinion for EPO Application No. 07758495.1, dated Apr. 29, 2010, 10 pgs.
“Intel I/O Acceleration Technology,” Date Unknown, pp. 1-2.
Patent Cooperation Treaty, Notification of International Search Report and Written Opinion mailed Jul. 20, 2007 in international application No. PCT/US2006/047234.
U.S. Patent and Trademark Office, Office Action mailed Sep. 17, 2008 with Reply filed on Dec. 16, 2008 in U.S. Appl. No. 11/316,772.
U.S. Patent and Trademark Office, Office Action Apr. 15, 2009 with Reply filed on Jul. 13, 2009 in U.S. Appl. No. 11/316,772.
U.S. Patent and Trademark Office, Office Action mailed Oct. 15, 2009 with Reply filed omn Jan. 14, 2010 in U.S. Appl. No. 11/316,772.
U.S. Patent and Trademark Office, Office Action mailed Apr. 26, 2010 with Reply filed on Jul. 22, 2010 in U.S. Appl. No. 11/316,772.
Chinese Patent Office, Office Action dated Feb. 5, 2010, in Chinese patent application serial No. 200680042242.0.
U.S. Patent and Trademark Office, Notice of Allowance mailed Oct. 14, 2010 in U.S. Appl. No. 11/316,772.
Taiwanese Patent Office, Office Action mailed Dec. 20, 2010 in Taiwanese patent application No. 095146431.
U.S. Patent and Trademark Office, Notice of Allowance Mailed Feb. 2, 2010 in U.S. Appl. No. 11/316,772.

Affiliated with

Also associated with

Rating

Validating data using processor instructions does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Validating data using processor instructions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Validating data using processor instructions will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2717449