Valid flag for disabling allocation of accelerated graphics port

Details Valid flag for disabling allocation of accelerated graphics port Valid flag for disabling allocation of accelerated graphics port

1997-09-09

1999-06-22

Tung, Kee M.

Computer graphics processing and selective visual display system

Computer graphic processing system

Plural graphics processors

345514, 345520, 345521, 345515, 711207, G06F 1516

Patent

active

059147270

ABSTRACT:
A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing. The required amount of virtual memory address space for AGP is determined from the AGP device and the information is put into a register of the core logic so that the computer system software may allocate the required amount of memory and assign a base address thereto during computer system startup or POST. An AGP Valid bit is set to indicate whether an AGP device is present or not. If the AGP device is not present, then no virtual memory address space is allocated during the computer system startup.

REFERENCES:
patent: 5802568 (1998-09-01), Csoppenszky
patent: 5812789 (1998-09-01), Diaz et al.

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