Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2001-04-20
2003-03-04
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S710000, C257S774000, C257S784000, C257S701000, C257S728000, C257S703000, C257S779000
Reexamination Certificate
active
06528875
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to packages for semiconductor chips or other electronic devices.
2. Description of the Related Art
Vacuum sealed packages are used for many types of semiconductor chips including, for example, micro-electromechanical (MEM) chips used in fiber optic applications. A typical vacuum sealed package for a semiconductor chip includes an internal leadframe, which functions as a substrate for the package. The leadframe includes a central metal die pad and a plurality of leads that radiate outward from the die pad. The semiconductor chip is mounted on the die pad and is electrically connected to the leads. In particular, the chip includes a plurality of bond pads, each of which is electrically connected by a bond wire or the like to a bond finger that is at an inner end of one of the leads. An outer portion of each lead extends outward from the chip, and serves as an input/output (I/O) terminal for the package. The outer portion of the leads may be bent into various configurations, such as a J lead configuration or a gull wing configuration.
In order to maintain vacuum, a metal enclosure is used. The chip and die pad are contained within the metal enclosure, with each of the leads projecting outward through a respective aperture in a peripheral side of the metal enclosure. Each aperture is sealed around the lead extending therethrough by reflowed glass, which also serves to electrically isolate the lead from the metal enclosure. A metal tube extends into the interior of the enclosure where the chip is located. After the package is assembled, a vacuum is pulled in the interior of the metal enclosure through the tube, and then the tube is crimped or soldered to seal it and maintain the vacuum.
The above-described package has numerous drawbacks. First, it is expensive to make, in part because of the need for the sealed metal enclosure. Second, the number of leads that can be accommodated is limited. Third, the package configuration does not allow for many lead configurations that are commonly used for other types of packages, such as ball grid array (BGA), land grid array (LGA), and leadless chip carriers (LCC). Fourth, the heat dissipation capability of the package is limited. Accordingly, an improved, more versatile vacuum sealed package is needed.
SUMMARY
The present invention describes a vacuum sealed package that includes a substrate that has a conductive interconnect pattern extending through the substrate to external I/O terminals. For instance, the substrate may be a multilayer ceramic substrate. A chip is mounted on the substrate and is electrically connected to the interconnect pattern of the substrate. A lid is bonded to the substrate and defines, together with the substrate, a cavity enclosing the chip. The substrate also includes at least one hole, which is at least partially lined with a metal coating, extending through the substrate and into the cavity where the chip is enclosed. The hole is blocked with a plug, such that the cavity is held in an evacuated state.
In one embodiment of an assembly method, such a vacuum sealed package is made by providing a substrate including a conductive interconnect pattern that includes external I/O terminals. The substrate also includes at least one vent hole, which extends through the substrate. The vent hole is at least partially lined with a metal coating. The substrate also includes, adjacent to the vent hole, a metal preform, which is fused to the metal coating of the vent hole. For instance, the substrate may be a multilayer ceramic substrate. A chip is mounted onto the substrate and is electrically connected to the interconnect pattern of the substrate. A lid is bonded to the substrate such that the lid and substrate together define a cavity enclosing the chip. The vent hole, which extends through the substrate, extends into the cavity. The cavity is evacuated through the vent hole. The substrate is then heated so as to melt the metal preform, which thereupon flows into the vent hole to form a plug that is fused to the metal coating of the vent hole. The plug seals the cavity in an evacuated state.
These and other aspects and features of the present invention will be better understood in view of the following detailed description of the exemplary embodiments and the drawings thereof.
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Glenn Thomas P.
Hollaway Roy D.
Webster Steven
Amkor Technology Inc.
Date Celisa
Parekh Nitin
Parsons James E.
Skjerven Morrill LLP
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