Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-04-24
2008-10-07
Lane, Jack A (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S167000, C712S216000, C717S151000, C717S154000, C717S159000
Reexamination Certificate
active
07434002
ABSTRACT:
In a method of optimizing utilization of a shared cache, a set of locations in the cache is probed. The probing takes place while an observed process is running, descheduled, or interrupted. It is determined which portions of the cache are utilized by the observed process. Utilization of the cache is optimized based on result of the determination of which portions of the cache are utilized by the observed process.
REFERENCES:
patent: 6564297 (2003-05-01), Kosche
patent: 7139872 (2006-11-01), Bachmat
patent: 2003/0033480 (2003-02-01), Jeremiassen
patent: 2006/0143421 (2006-06-01), Subramoney et al.
Waldspurger Carl
Zedlewski John
Lane Jack A
Madnawat Rajeev
Pearce Jeffrey
VMware, Inc.
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