Utilization of MACRO power routing area for buffer insertion

Details Utilization of MACRO power routing area for buffer insertion Utilization of MACRO power routing area for buffer insertion

2005-02-15

2005-02-15

Chen, Jack (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

C257S203000, C257S208000, C257S210000, C257S211000, C257S691000, C257S698000, C257S750000, C257S774000

Reexamination Certificate

active

06855967

ABSTRACT:
A structure and a method for forming buffer cells in power line areas between macro cell in a macro block area. In a power line level, a pin is formed between VSS and VDD lines. The pin is connected to the buffer cell. Next a signal line layer is formed and the signal line is connected to the pin and to a driver. In a first embodiment the driver is formed in a standard cell area. In a second embodiment, the driver is formed in a macro cell. A signal line is connected to the pin and the driver.

REFERENCES:
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patent: 5313079 (1994-05-01), Brasen et al.
patent: 5341049 (1994-08-01), Shimizu et al.
patent: 5343058 (1994-08-01), Shiffer, II
patent: 5619048 (1997-04-01), Yokota et al.
patent: 5869900 (1999-02-01), Crafts
patent: 5923059 (1999-07-01), Gheewala

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