Utilization of die repattern layers for die internal connections

Details Utilization of die repattern layers for die internal connections Utilization of die repattern layers for die internal connections

1999-04-07

2000-09-26

Smith, Matthew

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438601, 438597, 438598, H01L 2144

Patent

active

061241954

ABSTRACT:
The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bumps sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.

REFERENCES:
patent: 3461357 (1969-08-01), Mutter et al.
patent: 3809625 (1974-05-01), Brown et al.
patent: 3881971 (1975-05-01), Greer et al.
patent: 4808552 (1989-02-01), Anderson
patent: 4988423 (1991-01-01), Yamamoto et al.
patent: 5106461 (1992-04-01), Volfson et al.
patent: 5130768 (1992-07-01), Wu et al.
patent: 5231590 (1993-07-01), Kumar et al.
patent: 5244837 (1993-09-01), Dennison
patent: 5341310 (1994-08-01), Gould et al.
patent: 5414637 (1995-05-01), Bertin et al.
patent: 5495397 (1996-02-01), Davidson et al.
patent: 5506172 (1996-04-01), Tang
patent: 5523253 (1996-06-01), Gilmour et al.
patent: 5523626 (1996-06-01), Hayashi et al.
patent: 5534465 (1996-07-01), Frye et al.
patent: 5570504 (1996-11-01), DiStefano et al.
patent: 5597470 (1997-01-01), Karavakis et al.
patent: 5619017 (1997-04-01), Distefano et al.
patent: 5632631 (1997-05-01), Fjelstad et al.
patent: 5640761 (1997-06-01), DiStefano et al.
patent: 5666007 (1997-09-01), Chung
patent: 5679609 (1997-10-01), Aimi et al.
patent: 5688721 (1997-11-01), Johnson
patent: 5751031 (1998-05-01), Thompson et al.
patent: 5904556 (1999-05-01), Suzuki et al.

Affiliated with

Also associated with

Rating

Utilization of die repattern layers for die internal connections does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Utilization of die repattern layers for die internal connections, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Utilization of die repattern layers for die internal connections will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2099726