Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2006-07-17
2010-10-12
Chace, Christian P (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S006000, C711S207000, C718S001000, C719S319000
Reexamination Certificate
active
07814287
ABSTRACT:
A method and system for using writeable page tables to increase performance of memory address translation in computing environments utilizing a hypervisor. Guest operating systems are given temporary write-access to a page table page after the system confirms that such page is not part of the current address space (i.e., confirming that the page is part of a different page table from the one that is currently in use, such as a different user-space process). Alternatively, if the page is part of the currently running page table, the system invalidates the appropriate entry in the root page directory, thus “unlinking” it, and ensuring that the appropriate region of virtual address space is flushed from the translation lookaside buffer (TLB) in the current CPU and others that may be using it. After giving the OS write-access, the page is added to a validation queue. Validation of all 1024 entries and “re-hooking” of the page occurs whenever a page fault is taken due to the page being unhooked, or before context switching to another page table.
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Chace Christian P
Choate Hall & Stewart LLP
Namazi Mehdi
XenSource, Inc.
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