Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-11-14
2006-11-14
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000, C711S003000, C711S113000, C711S118000, C711S119000, C711S142000, C711S146000, C370S432000, C370S394000
Reexamination Certificate
active
07136969
ABSTRACT:
Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each processor is an endpoint having its own local cache storage in which portions of global memory may be locally cached. A write through caching technique is described. Each local cache line of data of each processor is either in an invalid or a shared state. When a write to global memory is performed by a processor (write miss or a write hit), the following are performed atomically: the global memory is updated, other processor's local cache lines of the data are invalidated, verification of invalidation is received by the processor, and the processor's local copy is updated. Other processors' cache lines are invalidated by transmission of an invalidate command by the processor. A processor updates its local cache lines upon the next read miss or write miss of the updated cacheable global memory.
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Chalmer Steven R.
McClure Steven T.
Niver Brett D.
Chery Mardochee
EMC Corporation
Muirhead and Saturnelli LLC
Padmanabhan Mano
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