Using silicide cap as an etch stop for multilayer metal process

Details Using silicide cap as an etch stop for multilayer metal process Using silicide cap as an etch stop for multilayer metal process

1998-09-03

2000-09-12

Bowers, Charles

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438627, 438643, 438630, 438649, 438706, 438712, 438721, 438738, 438704, 438637, H01L 21302, H01L 214763

Patent

active

061177938

ABSTRACT:
A layered trace configuration comprising a conductive trace capped with a silicide material which allows for removal of oxide polymer residues forming in vias used for interlayer contacts in a multilayer semiconductor device and eliminates or greatly reduces the formation of metal polymer residues in the vias. The formation of an interlayer contact according to one embodiment of the present invention comprises providing a trace formed on a semiconductor substrate and a silicide layer capping the conductive layer. An interlayer dielectric is deposited over the silicide capped trace and the substrate. A via is etched through the interlayer dielectric, wherein the etch is selectively stopped on the silicide layer. Any residue forming in the via is removed and a conductive material is deposited in the via to form the interlayer contact.

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