Using run-time generated instructions in processors...

Details Using run-time generated instructions in processors... Using run-time generated instructions in processors...

2007-07-24

2007-07-24

Elmore, Reba I. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Memory configuring

C711S166000, C711S172000

Reexamination Certificate

active

10882455

ABSTRACT:
The processor typically uses address registers having a particular bit width to access lines within an address space. The bit width limits the address space to a particular size. Techniques are provided for expanding the allowed address bit width and the corresponding address space size by using immediate addressing. Mechanisms allow the run time generation of instructions that can access an array of addresses of varying size, providing a way of implementing address spaces that are not limited by the bit width of address registers.

REFERENCES:
patent: 5903772 (1999-05-01), White et al.
patent: 6952754 (2005-10-01), O'Connor et al.
patent: 2005/0055539 (2005-03-01), Pechanek et al.

Affiliated with

Also associated with

Rating

Using run-time generated instructions in processors... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Using run-time generated instructions in processors..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Using run-time generated instructions in processors... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3760104