Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2000-05-01
2003-11-11
McLean-Mayo, Kimberly (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S141000
Reexamination Certificate
active
06647469
ABSTRACT:
TECHNICAL FIELD
This invention relates generally to computer memory systems and more particularly to an access method for reading from a shared memory to an I/O device.
BACKGROUND
In a computer system, problems often arise when more than one device attempts to access information stored in a memory location. While multiple devices can access a single memory location, if one of the accessing devices attempts to update the information in the memory location, without informing the other devices who also have access to the specific memory location, data mismatches may occur resulting in a loss of data coherency.
To speed access and minimize data latency, some memory accessing devices use a local memory cache. Within the local cache the device may store a copy of information which it has recently accessed. Thus, there may be several copies of information scattered throughout a system.
When a system implements local cache, main and cache memory may be organized into cache lines. A cache line is typically 64 bytes of data. Therefore, when a device attempts to access a specific memory location the cache controller first searches its local cache to determine if it already has a copy of the information available. If a copy of the requested memory location is not currently stored in the local cache, the cache controller attempts to obtain a copy of the cache line from the system memory controller. If the information is available in the local cache, the device will use the information in the local cache. Issues arise when multiple devices attempt to access the same cache line, and each device stores copies of this information in local cache. Not only must access conflicts be resolved, but procedures must be implemented to ensure coherency of the various copies of the data contained in the multiple caches and in the main memory.
Numerous protocols exist which maintain cache coherency across multiple caches and main memory. One such protocol is called MESI. MESI protocol, which is described in detail in M. Papamarcos and J. Patel, “A Low Overhead Coherent Solution for Multiprocessors with Private Cache Memories,” in Proceedings of the 11
th
International Symposium on Computer Architecture, IEEE, New York (1984), pp. 348-354, incorporated herein by reference. MESI stands for Modified, Exclusive, Shared, Invalid. Under the MESI protocol, a cache line is categorized according to its use. A modified cache line indicates that the particular line has been written to by the cache that is the current owner of the line. An exclusive cache line indicates that a cache has exclusive ownership of the cache line, which will allow the cache controller to modify the cache line. A shared cache line indicates that one, or more than one, cache(s) have ownership of the line. A shared cache line is considered read only and any device under the cache may read the line but no one is allowed to write to the cache. A cache line with no owner identifies a cache line whose data may not be valid since the cache no longer owns the cache line.
While MESI is a standard term in the industry, other classifications or nomenclature are frequency employed. Modified cache lines are typically referred to as private dirty. Exclusive cache lines are typically referred to as private cache lines. Private cache lines which have not been updated are typically referred to as private clean cache lines.
If a specific device requires access to a specific memory location it will check its local cache to determine if the information is available there. If the information is not currently contained within the local cache, the cache controller will go to main memory to access the information. Before requesting the cache line from the system memory controller, the cache controller decides what type of ownership for the line it will seek (i.e. shared, private, etc.). If a cache wants private ownership of a cache line, the system memory controller will ensure that no cache has the same line. The system memory controller will not allow any other cache to get ownership of this line so the cache's access to the line will be private. If the cache's access to the line is shared, more than one cache may have the same line as shared simultaneously.
A cache must have private or exclusive ownership of a cache line to modify the line. That is, other copies may not be relied upon as being valid until after the data is modified and an updated version is supplied. If the cache line is currently categorized as read only, the cache which needs to update the information must make a request to the system memory controller, for exclusive access to the cache line. The system memory controller then identifies any other caches having access to the cache line, and makes the necessary arrangements for the other caches to relinquish access and for the requesting cache to have exclusive use of the cache line.
One method for a cache to obtain the exclusive use of a cache line is for the memory controller to invalidate other copies of the cache line currently in use. Once other caches' access to the cache line has been invalidated, the remaining cache has exclusive use of the cache line and can update the cache line accordingly.
One of the methods to implement cache coherency is a directory-based system where rather than sending each transaction to every other agent or other processor in the system a table is maintained for each cache line which indicates which agent(s) have the cache line. The system memory controller consults with the directory to see the status of the cache line before it allows a cache to get data. For example, another cache has the cache line as private, the memory controller recalls the cache line from the original owner.
A device first checks its local cache to determine whether the information is available. If the information it requires is not locally available, the cache controller servicing the device sends a read request for shared ownership of the cache line via the system interconnect fabric to the system memory controller. If the requested cache line is shared or is not in use by any other cache, the system memory controller sends the data from main memory to the requesting cache directory reflecting the new owner of the cache line in shared mode. Once the requesting device has completed its use of the cache line, the cache controller sends a message relinquishing ownership of the cache line to the system memory controller. Upon receipt of his message the system memory controller removes the cache as a shared owner from its directory tag. If the cache controller had requested private access to the cache line but had updated the information stored within the cache line, the cache controller also sends updated information to the system memory controller. Each of these transactions between the cache controller and the system memory controller consume a portion of the interconnect fabric bandwidth. Additionally the system memory controller bandwidth is also affected by these transactions. A reduction in the number of steps required for the cache controller to acquire and relinquish ownership of the cache line would provide a corresponding improvement to overall system performance.
Data requested and accessed by the cache controller can be one of several types. First, the cache controller request and memory access can be associated with payload data. Payload data consists of a large data transfer so that it is often handled as blocks of 1 to 4 KB of data. A second type of data that can be requested and accessed by the cache controller is control data and is generally smaller in size. This information is typically between 4 and 32 KB and can be accommodated in one cache line for most applications.
In addition to the shared and private memory requests discussed previously, a third type of access to information stored in system memory exists. A “read current” transaction results in the requesting cache controllers receiving coherent data of the cache line at the time of the request but does not affect the ownership of the cache lin
Cowan Joe P.
Das Sharma Debendra
Ebner Sharon M.
Jackson Carl H.
Wickeraad John A.
Hewlett--Packard Development Company, L.P.
McLean-Mayo Kimberly
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