Using oxynitride spacer to reduce parasitic capacitance in...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE21626

Reexamination Certificate

active

07667275

ABSTRACT:
A complementary metal oxide semiconductor (CMOS) device has a substrate100, a gate structure108disposed atop the substrate, and spacers250, deposited on opposite sides of the gate structure108to govern formation of deep source drain regions S, D in the substrate. Spacers250are formed of an oxynitride (SiOxNyCz) wherein x and y are non-zero but z may be zero or greater; such oxynitride spacers reduce parasitic capacitance, thus improving device performance. A method of fabricating a portion of a complementary metal oxide semiconductor (CMOS) device involves providing a substrate100, forming a gate structure108over the substrate, depositing a first layer104atop the substrate on opposite sides of the gate structure to govern formation of deep source drain regions in the substrate, depositing an oxynitride (SiOxNyCz) layer250atop the first layer (in which x and y are non-zero but z may be zero or greater), depositing a second layer112atop the oxynitride layer, and depositing a nitride layer114B atop the second layer.

REFERENCES:
patent: 6677201 (2004-01-01), Bu et al.
patent: 6743705 (2004-06-01), Mehrotra et al.
patent: 2002/0055230 (2002-05-01), Chang
patent: 2002/0140100 (2002-10-01), Yokoyama
patent: 2002/0182795 (2002-12-01), Bae et al.
patent: 2003/0085436 (2003-05-01), Moore

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