Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
1999-11-12
2002-09-17
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S017000, C710S019000, C710S023000, C710S028000, C710S029000, C710S037000, C710S200000, C711S100000, C711S147000, C711S150000, C711S152000, C711S153000, C711S154000, C711S156000, C711S163000, C711S168000, C711S210000
Reexamination Certificate
active
06453370
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains generally to computing systems. More specifically, the present invention relates to a providing universal access to shared resources in a computing system such as a multi-processor computer systems.
BACKGROUND OF THE INVENTION
In a basic computer system, a central processing unit, or CPU, operates in accordance with a pre-determined program or set of instructions stored within an associated memory. In addition to the stored instruction set or program under which the processor operates, memory space, either within the processor memory or in an associated additional memory, is provided to facilitate the central processor's manipulation of information during processing. The additional memory provides for the storage of information created by the processor as well as the storage of information on a temporary, or “scratchpad”, basis which the processor uses in order to carry out the program. In addition, the associated memory provides locations in which output information from the processor's operating set of instructions is placed in order to be available for the system's output device(s).
In systems in which many components (processors, hard drive, etc) must share a common bus in order to access memory there is a high probability of memory access conflicts. Especially in the case of multiprocessor computer systems, and the like, in which different processors are simultaneously in operation, access to memory or other shared resources becomes complex. Since it is likely that each of the processors or processor systems may require access to the same memory simultaneously, conflicts between processors will generally be unavoidable. Essentially, the operation of two or more processors or processor systems periodically results in overlap of the memory commands with respect to a common memory, or other shared resource, in the multi-processor computer system.
Conventional approaches to solving the problem of conflicting memory access requests to a shared memory include, in one case, complete redundancy of the memories used for each of the processors, and isolation of the processor systems. However, this approach to solving the problem of conflicting memory access requests often defeats the intended advantage of the multiple processor system. Such multiple processor systems are most efficient if operated in such a manner as to provide parallel computing operations upon the same data in which one processor supports the operation of the other. Conventionally, such processor systems may be either time shared in which the processors compete for access to a shared resource, such as memory, or the processor systems may be dual ported in which each processor has its own memory bus, for example, where one is queued while the other is given access.
Various approaches have been used to avoid the above described conflict problems. In one approach, the avoidance of conflicts is accomplished by sequentially operating the processors or by time sharing the processors. In this way, the processors simply “take turns” accessing the shared resource in order to avoid conflict. Such systems commonly include “passing the ring” or “token systems” in which the potentially conflicting processors are simply polled by the system in accordance with a pre-determined sequences similar to passing a ring about a group of users.
Unfortunately, use of sequential processor access methodologies imposes a significant limitation upon the operation of the overall computer system. This limitation arises from the fact that a substantial time is used by the system in polling the competing processors. In addition, in the case where only a single processor is operating and requires access to the shared memory, for example, a delay occurs whenever the processor accesses the shared resource following each memory cycle as the system steps through the access sequence.
Another conventional approach to conflict avoidance relies upon establishing priorities amongst the processors in the computer system. One such arrangement provides every processor assigned to it a priority of system importance. The memory controller simply provides access to the highest priority processor every time a conflict occur. For example, in a two processor system, a first and a second processor access a shared memory which is typically a dynamic RAM (DRAM) type memory device which requires periodic refreshing of the memory maintain stored data. Generally, the DRAM type memory is refreshed by a separate independent refresh system. In such a multi-processor system, both the processors and the refresh system compete for access to the common memory. A system memory controller will process memory access request conflicts, or commands, as determined by the various priorities assigned to the processors and the refresh system. While such systems resolve conflicts and are somewhat more efficient than pure sequential conflict avoidance systems, they still suffer from lack of flexibility.
Another approach to conflict resolution involves decision-making capabilities incorporated in the memory controller. Unfortunately, because the decision making portions of the memory controller are operated under the control and timing of a clock system, a problem arises in that substantial time is utilized in performing the actual decision making before the memory controller can grant access to the common memory.
Unfortunately, this problem of performing the actual decision making substantially erodes the capability of conventional memory controllers granting access to multi-bank type memory systems. In multi-bank type memory systems, the actual memory core is departmentalized into specific regions, or banks, in which data to be retrieved is stored. Although providing faster and more efficient memory access, the complexity required of conventional memory controllers in coping with a multi-bank memory device substantially slows the overall access time of the system as a whole.
In view of the foregoing, it should be apparent that a method of speeding up a memory access of a memory page included in a memory bank in a multi-bank type memory by a memory controller is desired.
SUMMARY OF THE INVENTION
In one embodiment of the invention, a method of using bank tag registers in a multi-bank memory device to avoid a background operation collision is described. In the described embodiment, the memory device is capable of non-sequential access and is included in a memory bank in a multi-bank type memory. A memory controller coupled to the multi-bank memory device includes a plurality of bank registers each of which is associated with one of the plurality of memory banks, such that a particular bank register associated with a particular bank is arranged to store a particular bank number that defines the number of the bank in which information is stored, a bank status that indicates the status of the particular bank, and a bank counter and an adjustable bank number comparator unit coupled to each of the plurality of bank registers. The method is performed by receiving an incoming system address request, wherein the incoming system address request includes a requested bank number such that operating characteristics of the particular bank are used to configure the adjustable comparator, locating a bank register corresponding to the requested bank number by the bank number comparator, determining the bank status of the bank associated with the requested bank number, determining a bank entry condition based upon the determined bank status, and accessing the requested memory bank when the bank entry condition identifies that the requested bank is open.
In another embodiment of the invention, a method of using bank tag registers in a multi-bank memory device to avoid a background operation collision is described. In the described embodiment, the memory device is capable of non-sequential access and is included in a memory bank in a multi-bank type memory. A memory controller coupled to the multi-bank memory device includes a plurality of
Stracovsky Henry
Szabelski Piotr
Beyer Weaver & Thomas LLP
Gaffin Jeffrey
Infineion Technologies AG
Nguyen Tanh Q.
LandOfFree
Using of bank tag registers to avoid a background operation... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Using of bank tag registers to avoid a background operation..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Using of bank tag registers to avoid a background operation... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2909167