Using linked list for caches with variable length data

Details Using linked list for caches with variable length data Using linked list for caches with variable length data

2005-02-08

2005-02-08

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

Addressing cache memories

C711S119000, C711S206000

Reexamination Certificate

active

06854033

ABSTRACT:
In general, the cache structure overcomes the deficiency of wasted tag space and reduces associativity. The method provides for storing a single tag along with a pointer to the actual data which is stored in a separate array which includes several lines. Each data block may have a variable length and occupy several lines. These lines are linked together to form a linked list. An invalidation mechanism allows invalidation of lines of the same data block, increasing data efficiency.

REFERENCES:
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patent: 6341325 (2002-01-01), Franaszek et al.
patent: 6353871 (2002-03-01), Benveniste et al.
patent: 6430666 (2002-08-01), Roth
patent: 6453319 (2002-09-01), Mattis et al.

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