Using FET switches for large memory arrays

Details Using FET switches for large memory arrays Using FET switches for large memory arrays

1998-04-01

2001-05-15

Yoo, Do Hyun (Department: 2185)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C365S189020

Reexamination Certificate

active

06233650

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to microprocessor systems. In particular, the invention relates to use of field-effect transistor (FET) switches for large memory arrays.
2. Description of Related Art
High performance microprocessor systems typically involve a large number of high speed memories. Interfacing these memories to the processor typically includes connecting all the data lines of the memory devices to the processor's data bus lines. Connecting a large number of data lines to the processor's data bus creates a number of problems. The major problem is the high capacitive load caused by a large number of data lines tied together. Four dynamic random access memory (DRAM) modules can have up to 80 picofarads (pf) on the data lines typically. A large capacitive loading incurs long delay time along the signal lines. At high frequencies, the delay time causes unacceptable performance. Another problem is the high power consumption caused by the output drivers. Since input/output (I/O) buffer power is directly related to the capacitive load, a high capacitive loading results in high power consumption. Lastly, the large capacitive loading limits the flexibility of running the signal traces on a printed circuit board.
Therefore there is a need in the technology to provide an efficient method and apparatus to interface a large memory array to a high-performance processor.
SUMMARY OF THE INVENTION
The present invention discloses a method and apparatus for interfacing a memory array to a memory controller using a field-effect transistor (FET) switch. The memory controller has a bus which comprises a plurality of signal lines. The memory array is coupled to the memory controller. The memory array is divided into N groups of memory devices; each group has K memory devices. K memory devices in each of the N groups share memory signal lines. The FET switch couples the bus to one of the N groups of the shared memory signal lines at different times in response to a switch control indication.


REFERENCES:
patent: 3654394 (1972-04-01), Gordon
patent: 4513368 (1985-04-01), Houseman
patent: 4645944 (1987-02-01), Uya
patent: 4985703 (1991-01-01), Kaneyama
patent: 5261068 (1993-11-01), Gaskins et al.
patent: 5289062 (1994-02-01), Wyland

Affiliated with

Also associated with

Rating

Using FET switches for large memory arrays does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Using FET switches for large memory arrays, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Using FET switches for large memory arrays will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2450041