Using a model specific register as a base I/O address...

Details Using a model specific register as a base I/O address... Using a model specific register as a base I/O address...

2000-01-03

2004-03-23

Lee, Thomas (Department: 2185)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

C710S003000, C710S009000, C711S202000

Reexamination Certificate

active

06711673

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to microprocessors and more particularly to accessing registers on a microprocessor, which are mapped into input/output memory space.
2. Description of the Related Art
In traditional x86 architectures, the processor has both memory and input/output (I/O) mapped address space. With I/O mapped I/O, registers of peripheral devices are accessed through I/O instructions, which access the registers (also referred to herein as ports) in I/O address space. A signal line (M/IO) indicates to logic external to the processor whether the processor is addressing an I/O mapped I/O port during execution of an I/O instruction or whether the processor is accessing memory (or a memory-mapped I/O port) as a result of an instruction fetch or an instruction that loads or stores data.
As levels of integration continue to increase in processors, additional I/O like functions are expected to be added to processors. It is possible that the functions could be accessed through model specific registers (MSRs). In x86 microprocessors such as the AMD-K6®-III microprocessor, model specific registers (MSRs) provide a way to utilize capabilities that may be unique to a particular microprocessor model. Examples of model-specific registers are test registers such as cache test registers. Those registers may be accessed using the read MSR (RDMSR) and write MSR WRMSR) instructions. The RDMSR instruction takes the value from an MSR specified in a first general purpose register (the “ecx” register), and places the high-order bits in a second general purpose register (the “edx” register) and the low-order bits in a third general purpose register (the “eax” register). A “WRMSR” instruction performs a write to an MSR using the same registers.
However, the use of MSRs may be undesirable because such use may lead to nonstandard solutions across different processor models. In addition, access to such registers is restricted to software having a certain privilege level. Microprocessors and operating system software provide a privilege mode environment for application software and even some system management software, which restrict which registers are accessible to such software. For example, it is known to provide four levels of privilege (
0
-
3
) with
0
being the highest. In such an environment access to MSR registers may require the software to operate at the highest privilege level (also known as ring
0
). Thus, access to MSR registers through RDMSR and WRMSR instructions are limited to software operating at CPU Privilege Level=0, also referred to as ring
0
. Popular operating systems such as Windows based operating systems discourage if not forbid application and system management software from using privilege level
0
.
Another possible solution would be to provide additional I/O pins on the processor for the functions, so the functions could be viewed as discrete devices. However, that solution would undesirably increase processor pin count and/or potentially modify an industry standard processor pin configuration.
Therefore, it would be desirable to be able to locate additional functions in the processor as levels of integration increase, access those functions through ports mapped into I/O space and not restrict the software that accesses those registers.
SUMMARY OF THE INVENTION
Accordingly, I/O ports internal to a processor are provided that are mapped into traditional I/O address space and accessible by conventional I/O instructions.
In a first embodiment, the invention provides a method for accessing an input/output (I/O) register that is located within the processor and mapped into input/output (I/O) address space. The method includes providing a base address register in the processor and loading a base address into the base address register. The base address register may be a model specific register. The input/output register is accessed with an input/output instruction at an address determined according to the base address and an offset therefrom. In one embodiment, the base address register is accessible to software operating at a first privilege level but not by software operating at a second privilege level, while the I/O register is accessible to software operating at the second privilege level. The method may further include determining when an I/O access is made to an address within a predetermined address range, determined according to the base address and an offset therefrom and providing an indication thereof. The processor accesses the I/O register within the processor without causing an input/output bus cycle when the indication indicates the address is within the predetermined address range and generates an input/output bus cycle, for accessing an input/output register external to the processor, when the indication indicates the address is outside of the predetermined address range.
In another embodiment, the invention provides a processor that includes a base address register storing a base address. The base address register may be a model specific register. At least a first register internal to the processor is mapped into I/O address space and has an address located at an offset from the base address, the offset being greater than or equal to 0. The processor may further include a comparator coupled to compare a target address for an I/O instruction to an address range that includes the first register. The processor includes trap logic for suppressing an input/output bus cycle when the access is to the first register. In certain embodiments, the base address register is accessible to software operating at a first privilege level and not accessible to software operating at a second privilege level.


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