Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2000-01-31
2001-01-09
Auve, Glenn A. (Department: 2781)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
Reexamination Certificate
active
06173348
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This application relates to data communication and more particularly to optimizing a bus for personal computer data traffic.
2. Description of the Related Art
In current and future personal computer systems, two basic types of data are transferred between integrated circuits: isochronous data and asynchronous data. Isochronous data refers to data used in real-time data streams such as audio data or motion-picture video data. Asynchronous data is used for all other transfers, such as central processing unit (CPU) accesses to peripherals or bulk data transmissions from a hard drive into system memory.
At present, proper support for both kinds of data in computer systems is inadequate. For example, the peripheral component interface (PCI) bus, a major input/output bus in present computer architectures, does not support isochronous data. If a computer system gives asynchronous data priority or treats isochronous data as asynchronous data, then those functions relying on real time data, such as motion-picture video, may not function satisfactorily. Alternatively, if a computer system prioritizes isochronous data, then the performance of the computer system can suffer since the latency of asynchronous data becomes unacceptably long. As computer systems are called on to perform more and more real time activity, such as real time video, it becomes more critical that asynchronous and isochronous data be treated in a manner that prevents problems from occurring in the real time tasks without adversely effecting other aspects of computer performance. Thus, there exists a need to appropriately accommodate both kinds of data in present and future computer systems.
SUMMARY OF THE INVENTION
Accordingly, the invention provides a method and apparatus which guarantees isochronous data a specified amount of bandwidth and worst-case latency. Data is selectably transferred in either whole-bus or half-bus mode to increase bus efficiency. The bus protocol attempts to reduce latency for transfer of asynchronous data in order to improve system performance. At the beginning of a bus frame, the bus transfers data in asynchronous priority mode by prioritizing transfer of asynchronous data over isochronous data. Data may be transferred in whole-bus or half-bus modes according to bus utilization. According to the bus protocol, each bus inter face tracks the amount of isochronous data transmitted and the bus switches to isochronous priority mode if necessary to guarantee isochronous bandwidth for the frame. If the bus switches to isochronous priority mode, the bus stays in isochronous priority mode until all isochronous transfers are complete. When one side completes transfer of its isochronous data, it will relinquish its portion of the bus to the other device to complete transfer of isochronous data in whole-bus mode.
In a first embodiment, the invention provides a method for communicating information including asynchronous and isochronous data between a first device and a second device coupled by a bus. The method includes, selectably transferring the information over the bus in one of asynchronous priority mode and isochronous priority mode. Asynchronous priority mode gives priority to transfer of the asynchronous data and isochronous priority mode gives priority to transfer of the isochronous data. The method further includes selectably transferring the information over the bus in either whole-bus mode or half-bus mode.
In another embodiment, the invention provides an integrated circuit that includes a bus interface circuit coupled to a bus which has a local data portion and an external data portion. The bus interface circuit couples to the bas in a half-bus mode in a default mode to transmit data on the local data portion and to receive data over the external data portion of the bus. The bus interface, in response to first conditions, is coupled to transmit data or receive data in a whole-bus mode in which data is transmitted or received over both the local data portion and the external data portion. The integrated circuit is also responsive to second conditions to transfer data in one of asynchronous priority mode and isochronous priority mode, asynchronous priority mode giving priority to transfer of the asynchronous data and isochronous priority mode giving priority to transfer of the isochronous data.
REFERENCES:
patent: 5581745 (1996-12-01), Muraoka et al.
patent: 5613163 (1997-03-01), Marron et al.
patent: 5872944 (1999-02-01), Goldrain et al.
patent: 6032211 (2000-02-01), Hewitt
Intel Corporation, “Accelerated Graphics Port Interface Specification”, Revision 1.0, Jul. 31, 1996, pp. 1-152.
Wickelgren, Ingred J., “The Facts About Fire Wire”, IEEE Spectrum, Apr. 1997, pp. 20-25.
Glaskowsky, Peter N., “Cyrix Creates Ultimate CPU for Games”, Microdesign Resources, Dec. 8, 1997, pp. 16-18.
Gwennap, Linley, “MediaGX Targets Low-Cost PCs”, Microprocessor Report, vol. 11, No. 3, Mar. 10, 1997, pp. 1-6.
Compaq, Digital Equipment Corp., IBM PC Company, Intel, Microsoft, NEC, and Northern Telcom, “Universal Serial Bus Specification”, Revision 1.0, Jan. 15, 1996, pp. 3-268, particularly Chapters 4 and 5.
Advanced Micro Devices , Inc.
Auve Glenn A.
Zagorin O'Brien & Graham LLP
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