Using a change in doping of poly gate to permit placing both hig

Details Using a change in doping of poly gate to permit placing both hig Using a change in doping of poly gate to permit placing both hig

1993-04-29

1995-11-21

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 27, 437 34, 437 56, 437 57, 437 58, 437152, 257369, 257408, H01L 21265

Patent

active

054686660

ABSTRACT:
A semiconductor device having high and low voltage transistors on the same chip. High voltage NMOS transistor 76 comprises a polysilicon gate 40 doped at a first dopant level. Low voltage NMOS transistor comprises a polysilicon gate 44 doped at a second dopant level. The second dopant level is higher than the first. High voltage PMOS transistor 84 comprises a polysilicon gate 48 doped at a third dopant level. Low voltage PMOS transistor comprises a polysilicon gate 52 doped at a fourth dopant level. The fourth dopant level is higher than the third.

REFERENCES:
patent: 4764478 (1988-08-01), Hiruta
patent: 5047358 (1991-09-01), Kosiak et al.
patent: 5087582 (1992-02-01), Campbell et al.
patent: 5183773 (1993-02-01), Miyata
patent: 5234853 (1993-08-01), Ikemasu

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