Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1996-08-14
2002-02-19
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S392000
Reexamination Certificate
active
06348719
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to semiconductor processing and more specifically to using a change in doping of the polysilicon gate to permit placing both high voltage and low voltage transistors on the same chip.
BACKGROUND OF THE INVENTION
As the density of integrated circuits increases, it becomes necessary to shrink the dimensions of NMOS and PMOS transistors. Proper scaling of NMOS and PMOS transistors typically requires that the operating voltage be decreased as the gate oxide thickness is shrunk. Otherwise, the electric field will become too large in the gate oxide and, consequently, the gate oxide will eventually fail.
On the other hand, if the operating voltage is decreased, the device will no longer be compatible with most of the current packaged integrated circuits which operate at a standard voltage. For, instance, most circuits using CMOS transistors with gate lengths of 0.8 microns or more operate at 5.0V. When the gate length in decreased to 0.5 microns and the gate oxide thickness to 90-120 Å, the voltage is lowered to 3.3V in order to maintain reliability of the gate oxide. Thus, a device is needed that has input/output peripheral sections that operate at 5.0 V so that the device may be used in systems using other chips operating at 5.0 V while allowing other portions of the device to operate at 3.3 V. The same problem occurs when the gate length is reduced from 0.5 &mgr;m to 0.35 &mgr;m or 0.25 &mgr;m. At 0.35 &mgr;m, the voltage is reduced to 2.5V or lower in order to maintain the integrity of the gate oxide.
One method that has been used to overcome this problem uses longer gate lengths in the input/output CMOS transistors in order to minimize the hot carrier stress problem. However, gate insulator reliability may still be a problem due to the large electric field in the gate insulator.
Another method uses a thicker gate oxide for the input/output sections. This lowers the electric field in the high voltage CMOS transistors. However, this method requires a resist to be patterned on the gate oxide to remove the oxide from one portion of the chip and then strip the resist and grow the second gate oxide of a different thickness. As a result, defects and contamination may occur in the gate oxide.
Another approach uses two polysilicon layers. One polysilicon layer is placed over a first gate of one thickness. Next, a second gate oxide is grown and another polysilicon layer is deposited over the second gate oxide. This process however, adds to many additional process steps.
SUMMARY OF THE INVENTION
Generally, and in one form of the invention, a method for forming a semiconductor device having a semiconductor body is disclosed. A gate oxide is formed over a surface of the semiconductor body and a layer of polysilicon is deposited over the gate oxide. The polysilicon layer is patterned to expose the area where low voltage NMOS transistors are to be formed. The low voltage NMOS region is implanted with an n-type dopant at a first dopant level. The polysilicon layer may then be patterned to expose the ares where low voltage PMOS transistors are to be formed. The low voltage PMOS region may then be implanted with a p-type dopant at a second dopant level. The polysilicon layer and gate oxide are then etched to form at least one high voltage NMOS gate, at least one low voltage NMOS gate, and, optionally, at least one low voltage PMOS gate, and at least one high voltage PMOS gate. Note that the low voltage NMOS and PMOS transistor gates will already comprise doped polysilicon. The n+ source/drain regions, the high voltage NMOS gate and the low voltage NMOS gate are implanted with the n-type dopant at a third dopant level. The p+ source/drain regions, the high voltage PMOS gate and the low voltage PMOS gate may then be implanted with the p-type dopant at a fourth dopant level.
An advantage of the invention is in providing a semiconductor device comprising both high and low voltage transistors.
A further advantage of the invention is in providing a semiconductor device having both high and low voltage transistors that avoids gate insulator reliability problems.
A further advantage of the invention is in providing a semiconductor device having both high and low voltage transistors that does not require longer gate lengths in the high voltage transistors.
A further advantage of the invention is in providing a semiconductor device having high voltage transistor gates at one dopant level and low voltage transistor gates at a higher dopant level.
These and other advantages will be apparent to those skilled in the art having reference to this specification, in conjunction with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings:
FIG. 1
is a cross-sectional view of the preferred embodiment of the invention;
FIG. 2
is a cross-sectional view of semiconductor body used as the starting point for the fabrication of the preferred embodiment of the invention;
FIGS. 3
a-d
are cross-sectional views of the preferred embodiment of the invention during various fabrication steps;
FIGS. 4
a-b
are cross-sectional views of lightly and heavily doped poly gates, respectively;
FIGS. 5
a-b
are band diagrams over the active channel of PMOS transistors having lightly and heavily doped poly gates, respectively;
FIGS. 6
a-b
are C-V diagrams of NMOS and PMOS transistors, respectively, having a gate oxide of 120 Å;
FIGS. 7
a-b
are C-V diagrams of NMOS and PMOS transistors, respectively, having poly gates doped once during the source/drain implant;
FIGS. 8
a-b
are C-V diagrams of NMOS and PMOS transistors, respectively, having extra poly gate doping; and
FIG. 9
is cross-sectional view of an alternate preferred embodiment of the invention.
REFERENCES:
patent: 4472871 (1984-09-01), Green et al.
patent: 4559694 (1985-12-01), Yoh et al.
patent: 5214298 (1993-05-01), Yuan et al.
patent: 4056354 (1992-02-01), None
Honeycutt Gary C.
Navarro Arthur I.
Prenty Mark V.
Telecky Fred
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