User-controlled delay circuit for a programmable logic device

Details User-controlled delay circuit for a programmable logic device User-controlled delay circuit for a programmable logic device

1998-04-01

2000-11-21

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

327271, 327276, 327277, H03H 1126

Patent

active

061508632

ABSTRACT:
An input block is provided that includes a user-controlled, variable-delay input circuit. The input circuit is adapted to receive an input signal and to output a delayed version of the input signal on an output node. A number of control signals dictate the amount of delay imposed on the input signal. The control signals, and therefore the amount of delay, are established using a control-signal generator. The generator can be used to actively alter the delay. In one embodiment, the control signal generator is implemented as a feedback circuit that automatically matches the delay period of the delay circuit with the delay period of a distributed clock signal.

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"The Programmable Logic Data Book", Sep. 1996, pp. 4-24 to 4-29 available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
Xilinx Application Note XAPP056, entitled "System Design with New XC4000X I/O Features, v. 1.2", published Nov. 1997, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.

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