Use of voids between elements in semiconductor structures...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S315000, C257S316000, C257S317000, C257S318000

Reexamination Certificate

active

07045849

ABSTRACT:
A flash EEPROM or other type of memory cell array having adjacent charge storage elements is formed with a gas filled void between them in order to reduce the level of capacitive coupling between storage elements, thus reducing cross-coupling between charge storage elements and resulting errors occurring in the data read from the array.

REFERENCES:
patent: 4892753 (1990-01-01), Wang et al.
patent: 5043940 (1991-08-01), Harari
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harari
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5315541 (1994-05-01), Harari et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5570315 (1996-10-01), Tanaka et al.
patent: 5661053 (1997-08-01), Yuan
patent: 5712180 (1998-01-01), Guterman et al.
patent: 5734607 (1998-03-01), Sung et al.
patent: 5774397 (1998-06-01), Endoh et al.
patent: 5867429 (1999-02-01), Chen et al.
patent: 5869379 (1999-02-01), Gardner et al.
patent: 6013584 (2000-01-01), M'Saad
patent: 6046935 (2000-04-01), Takeuchi et al.
patent: 6057224 (2000-05-01), Bothra et al.
patent: 6103573 (2000-08-01), Harari et al.
patent: 6106678 (2000-08-01), Shufflebotham et al.
patent: 6110793 (2000-08-01), Lee et al.
patent: 6136687 (2000-10-01), Lee et al.
patent: 6151248 (2000-11-01), Harari et al.
patent: 6190981 (2001-02-01), Lin et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6281075 (2001-08-01), Yuan et al.
patent: 6303464 (2001-10-01), Gaw et al.
patent: 6335288 (2002-01-01), Kwan et al.
patent: 6350672 (2002-02-01), Sun
patent: 6413827 (2002-07-01), Farrar
patent: 6469339 (2002-10-01), Onakado et al.
patent: 2001/0003379 (2001-06-01), Seo
patent: 2003/0006448 (2003-01-01), Mehrad et al.
patent: 2003/0109093 (2003-06-01), Harari et al.
patent: 2003/0151069 (2003-08-01), Sugimae et al.
patent: WO 02/07213 (2002-01-01), None
Peters, Laura “Are Air Gaps Coming sooner Than We Think?”, Semiconductor International, www.reed-electronics.com/semiconductor/index.asp?layout=articlePrint&articleID=CA307349, Jul. 1, 2003, 2 pages.
Lee, Jae-Duk et al., “Effects of Parasitic Capacitance on NAND Flash Memory Cell Operation”, IEEE Non-Volatile Semiconductor Memory Workshop, Aug. 12-16, 2001, Monterey, CA, pp. 90-92.
Lee, Jae-Duk et al., “Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation”, IEEE Electron Device Letters, vol. 25, No. 5, May 2002.
Kynett, Virgil Niles et al., “An In-System Reprogrammable 256K CMOS Flash Memory”, IEEE International Solid-State Circuits Conference, Feb., 1988, pp. 132-133.
Qian, L.Q., et al., “High Density Plasma Deposition and Deep Submicron Gap Fill With Low Dielectric Constatn SiOF Films”, DUMIC Conference, Feb. 21-22, 1995, pp. 50-56.
Lee, B., et al., “Dielectric Planarization Techniques for Narrow Pitch Multilevel Interconnects”, V-MIC Conference, Jun. 15-16, 1987, pp. 85-92.
Nozaki, Takaaki et al., “A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application”, IEEE Journal of Solid-State Circuits, vol. 26, No. 4, Apr. 1991, pp. 497-501.
Eitan, Boaz et al., “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell”, IEEE Electron Device Letters, vol. 21, No. 11, Nov. 2000, pp. 543-545.
Chan, T.Y. et al., “A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device”, IEEE Electron Device Letters, vol. EDL-8, No. 3, Mar. 1987, pp. 93-95.
EPO/ISA, “Notification of Transmittal of the International Search Report and the Written Opinion of the International Searching Authority, or the Declaration”, Dec. 10, 2004, mailed in corresponding PCT/US2004/013986, 13 pages.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Use of voids between elements in semiconductor structures... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Use of voids between elements in semiconductor structures..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Use of voids between elements in semiconductor structures... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3553464

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.