Use of spacers as floating gates in EEPROM with doubled storage

Details Use of spacers as floating gates in EEPROM with doubled storage Use of spacers as floating gates in EEPROM with doubled storage

1996-04-22

1998-06-02

Wojciechowicz, Eward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257315, 257316, 257321, 257403, 438157, 438176, 438267, 438522, 438694, H01L 2972

Patent

active

057604355

ABSTRACT:
A method of forming a high density cell in electrically erasable and programmable read only memory (EEPROM) is disclosed. The doubling efficiency is achieved through providing two floating gates in a single cell, unlike what is found in prior art. While the polysilicon control gate is formed by conventional means, the floating gates are formed through a novel method of forming additional polysilicon spacers which are then coupled with lightly doped drain (LDD) regions to function as floating gates. Furthermore, the cell is turned on and off through the modulation of the LDD resistance and not through charge saturation methods of prior art. Finally, it is shown that through the use of two floating gates, rather than one, two bits of information can be stored in one cell with the concomitant advantage of doubled efficiency.

REFERENCES:
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patent: 5414287 (1995-05-01), Hong
patent: 5614747 (1997-03-01), Ahn et al.
S. Wolf, "Silicon Processing In The VLSI-vol. 2", Lattice Press, Sunset Beach, CA, pp. 632-634.

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