Use of source/drain asymmetry MOSFET devices in dynamic and...

Details Use of source/drain asymmetry MOSFET devices in dynamic and... Use of source/drain asymmetry MOSFET devices in dynamic and...

2001-05-18

2002-10-15

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C257S404000

Reexamination Certificate

active

06466489

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor devices and more particularly to CMOS circuits.
2. Description of Related Art
The design trade-off between low-power and signal strength in dynamic and analog circuits usually determines the selection of threshold voltage V
th
in the CMOS technology. However, the threshold voltage V
th
is not easily scalable with the continuous voltage and geometrical scaling in CMOS transistor technology.
Source/drain asymmetry effects in charge pumps embodied with CMOS transistors have been discussed in the literature, but all previous work has focused on the comparison with the symmetrical devices in the forward biasing directions. Parasitic RC elements and carrier transport in tailored channel electric fields have been studied. None of the previous work has proposed to use both biasing directions to achieve better dynamic and analog circuit design.
U.S. Pat. No. 4,439,692 of Beekmans et al. for “Feedback-Controlled Substrate Bias Generator” describes a charge pump with three diodes connected in series and a pair of capacitors which have one plate connected to the junctions between the diodes. The other plate of each capacitor is connected to voltage sources which alternate between high and low values with one voltage always being high when other voltage is low.
U.S. Pat. No. 5,081,371 of Wong for “Integrated Charge Pump Circuit with Back Bias Voltage Reduction” shows a charge pump with three NMOS transistors connected in a series by source to diode connections. The NMOS transistors which are connected as diodes with the gate shorted to the drain. There are three capacitors connected to the sources of the transistor with the two intermediate capacitors connected to clock signals which are 180° out of phase with each other as provided by inverter circuits driven by a common clock.
U.S. Pat. No. 5,386,151 of Folmsbee for “Low Voltage Charge Pumps Using P-Well Driven MOS Capacitors” describes the operation of a charge pump formed by diode connected nMOS FET devices with the gate shorted to the drain and MOS capacitors formed with a p-well acting as one plate thereof.
U.S. Pat. No. 5,589,697 of Smayling et al. for “Charge Pump Circuit with Capacitors” shows a series of Schottky diodes with one plate of a separate capacitor connected to the cathode of each of the diodes. The other plates of the capacitors are connected to alternate phase clock pulses generated by clock circuitry.
U.S. Pat. No. 5,524,266 of Tedrow et al. for “System Having Multiple Phase Boosted Charge Pumps with a Plurality of Stages” shows a charge pump circuit in which each stage includes a storage capacitor plus two FET devices which include a switching transistor and a control transistor. Either four or two different clock signals are employed in the embodiments shown.
U.S. Pat. No. 5,943,271 of Fujita for “Semiconductor Integrated Circuit Device” shows a modified Dickson type pMOS FET charge pump circuit with two clocks with different phases devices to bias a semiconductor substrate or a well.
Wu et al. “MOS Charge Pumps for Low-Voltage Operation” describes a traditional Dickson four stage charge pump in which MOSFET devices are connected as diodes, so that the charge thereon can be pumped. The paper describes other charge pumps for low-voltage operation, greater pumping gains, and higher output voltages that a Dickson charge pump. A first embodiment comprises a four-stage charge pump with static charge transfer switch (CTS) stages. Each stage includes at least two MOS devices connected in parallel. For each stage, in addition to the usual diode connected MOSFET transistor, there is a charge transfer switch (CTS) transistor connected in parallel with the diode connected transistor. The CTS transistors have their gate electrodes connected to the output of the next stage of the four-stage device. There is also a dynamic CTS transistor embodiment in which each CTS is controlled by a pair of pass transistors.
U.S. Pat. No. 6,191,963 of McPartland et al. for “Charge Pump with No Diode Drop at Output Stage” describes a charge pump with a series of stages with each stage including a transistor, a diode connected transistor, and a capacitor with the transistor and the diode connected transistor forming a charge transfer switch. The switches are controlled by alternately by inverted clock signals.
Charge pump circuits can boost the voltage on the wordlines (WL) of SRAM/DRAM devices, and provide large write/erase voltages for EEPROM and/or FLASH devices. For System-on-Chip (SoC) applications integrating various functional components with different voltage scaling, voltage multiplication is essential. Due to requirements for low-power, charge pumps need to be efficient in terms of power conversion and voltage multiplication. Conventional charge pumps and voltage multipliers are implemented by one-direction switches to push charges to a storage capacitor in a Dickson type charge pump circuit which is described in Wu et al. above.
FIG. 3
shows a prior art Dickson type of MOSFET charge pump circuit which can generate a voltage higher than a source voltage Vdd. The charge pump circuit of
FIG. 3
consists of N-MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) M
0
to M
4
connected in series with each MOSFET transistor connected as a diode by having its gate and drain connected/short circuited together at nodes N
0
-N
4
. Each of a set of charge pump capacitors C
1
-C
4
has one of its two terminals connected to the respective junction N
1
-N
4
of the gates and drains of the MOSFETs M
1
-M
4
, as well as, being connected to the sources of MOSFETs M
0
-M
3
. A fifth capacitor C
f
is connected to the source electrode of the FET M
4
.
FIG. 3
also shows the input waveforms of clocks &phgr;
1
and &phgr;
2
. The two clock inputs are operated 180° out of phase with respect to each other and are alternately applied to the other ends of the capacitors C
1
-
4
with the capacitors C
1
and C
3
connected through node N
6
to clock line &phgr;
1
and the capacitors C
2
and C
4
connected through node N
7
to clock line &phgr;
2
.
The drain and gate of the MOSFET M
1
are connected to the source voltage Vdd via an N-MOS FET M
0
. The source of the FET M
4
serves to provide the output voltage of the circuit. When the voltage on the node N
1
increases, the first FET M
0
can prevent a charge from migrating from the junction N
1
to the source voltage Vdd.
Principle of Operation of a Dickson Charge Pump Circuit
Referring to
FIG. 3
, assume that the threshold voltage of the n-MOSFET M
0
is Vt
0
, and that initially the clock &phgr;
1
is at a low level 0V). Then, the potential of the junction (or terminal) N
1
is (Vdd−Vt
0
). When the clock &phgr;
1
is switched to a high level at time t
1
, a potential at the junction N
1
can be expressed by the following equation:
(
Vdd−Vt
0
)+
V&phgr;
1
(
C
1
/(
C
1
+C
1S
))  Eq.(1)
where V&phgr;
1
is the voltage amplitude of the clock &phgr;
1
, and C
1S
is the parasitic capacitance (not shown in the figure).
At this point, the clock &phgr;
2
is at a low level (0V), but the potential on the junction N
2
is raised by the flow of charge (filling) the capacitor C
2
by discharging (emptying) charge Q
1
from the capacitor C
1
. The charge Q
1
migrates (is pumped) from the junction N
1
through to the junction N
2
into capacitor C
2
and increases the potential of the junction N
2
. The maximum potential of junction N
2
can be expressed as:
(
Vdd−Vt
0
)+
V&phgr;
1
(
C
1
/(
C
1
+C
1S
))−
Vt
1
  Eq.(2)
where Vt
1
is the threshold voltage of the MOSFET M
1
.
Thus, it can be shown that the circuit can boost the voltage by the increment V&phgr;(C/(C+C
S
))−Vt at each pumping stage.
The potential of the junction N
1
is lowered when the clock &phgr;
1
is switched to a low level (0V). At the same time, a charge corresponding to the charge Q
1
is fed from the power source Vdd to the junction N
1
via the MOSFET M
0
, thereby se

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