Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2001-03-20
2002-07-02
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S191000, C365S230030
Reexamination Certificate
active
06414902
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor memory devices, and more particularly to setup time in a synchronous memory device.
BACKGROUND OF THE INVENTION
Commands to a synchronous dynamic random access memory (SDRAM) are presented in the form of opcodes made up of combinations of low and high levels on the inputs at the time that the clock transitions (fires). These opcodes are scheduled to be valid for a specified minimum time (referred to as setup time) before the system clock fires to validate the command. A specified minimum hold time is also required. The combination of inputs may transition through a different command outside of setup and hold times without detriment since the commands are not normally acted upon until they are validated by a clock edge.
Every integrated circuit has a physical dimension which may require routing a signal from one end of a die to another end of the die. In a typical integrated circuit, some signals are routed across some parts of the circuit to prepare for a certain operation such as a read or write (read/write) operation.
A read/write operation of a typical SDRAM is carried out when a combination of input signals meet a predetermined condition when the system clock transitions high. One part of the integrated circuit in one end of the die analyzes the input signals and determines if their combination is valid for a read/write operation. Once there is valid combination, an enable signal will be issued from this part of the circuit. The enable signal then propagates to another part of the circuit, which could be located in another end of the die, to initiate the read/write operation. It is apparent that time is spent to wait for a signal to propagate from one end of the die to another. This is the propagation delay time that the circuit waits before it starts the read/write operation.
In order to improve the operation of a synchronous memory device, more particularly a read or a write operation, there is a need for a circuit and method which can use the setup time as a time to route a signal through a die so that the propagation delay is avoided or reduced.
SUMMARY OF THE INVENTION
The above-mentioned problem regarding propagation delay time during a setup time, especially during a read or a write operation of a synchronous memory will be addressed by the present invention and which will be understood by reading and studying the following specification. A setup time write and a setup time read/write circuit are described which allow a synchronous memory to fulfill the propagation delay time during a setup time of a read/write operation.
In particular, the present invention describes a memory device comprising a plurality of input signals, a clock signal having a setup time, a plurality of memory cells, and a circuit connected to the input signals and to the clock signal. The circuit is operable for preparing the memory device for an operation on the plurality of memory cells during setup time which is prior to the clock transition.
In another embodiment a synchronous memory device is described. The memory comprises input signals, a setup time write circuit connected to the input signals for producing an output signal to initiate a write operation prior to receiving a write enable signal during a setup time and a read/write setup time circuit connected to the input signals for producing a signal indicating a read or a write operation is being anticipated during a setup time. All operations performed prior to validation by a clock signal (CLK) are fully reversible since it is unknown if an opcode is to be acted upon or is just part of a transition to another state.
In yet another embodiment, a synchronous memory is described which comprises input signals and common input signals. A setup time write circuit connected to the input signals and the common input signals comprises an input circuit for producing an enable signal in response to the input signals, and an output circuit for producing an output signal in response to the common input signals during a setup time.
In yet another embodiment, a method of routing a signal through an integrated circuit is described. The method comprises the steps of receiving a clock signal, receiving input signals, defining a setup time period, producing an output signal in response to the input signals during the setup time, propagating the output signal during the setup time, producing an enable signal in response to the clock signal and the input signals during the setup time and latching the output signal after the setup time.
In yet another embodiment, a method of accessing a synchronous memory device is described. The method comprises the steps of receiving a clock signal, receiving input signals, defining a setup time period, producing an output signal in response to the input signals during the setup time, initiating a memory access during the setup time, generating an enable signal for a memory access during the setup time, receiving the enable signal for a memory access after the setup time and continuing the memory access after the setup time if the enable signal is valid for a memory access.
In yet another embodiment, a method of sending a signal through a die of a semiconductor memory device having memory cells and data write lines located in the proximity of the memory cells is described. The method comprises the steps of receiving a clock signal, determining a setup time, receiving data during the setup time, propagating the data to the data write lines during the setup time, and propagating data into the memory cells after the setup time.
REFERENCES:
patent: 5581512 (1996-12-01), Kitamura
patent: 5623453 (1997-04-01), Shinozaki
patent: 5703828 (1997-12-01), Park et al.
patent: 5867447 (1999-02-01), Kosikawa
patent: 6055208 (2000-04-01), Morgan et al.
Merritt Todd A.
Morgan Donald M.
Ho Hoai V.
Schwegman Lundberg Woessner & Kluth P.A.
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