Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including isolation structure
Reexamination Certificate
1999-09-03
2001-06-05
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Including isolation structure
C438S309000, C438S335000, C438S341000
Reexamination Certificate
active
06242313
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to increase the collector - emitter breakdown voltage of a high voltage bipolar device.
(2) Description of Prior Art
The use of BiCMOS, (bipolar—complimentary metal oxide semiconductor), semiconductor chips, used to achieve enhanced performance when compared to semiconductor chips fabricated using only CMOS devices, have again focused attention on bipolar devices. Applications demanding high bipolar breakdown voltages, such as the collector—emitter, or the BVceo parameter, have led to the use of a Buried layer Pinched Collector Bipolar, (BPCB), device, in which the collector—emitter breakdown can be as high as about 30 to 40 volts. Additional increases in BVceo can be achieved by deceasing the concentration of an N well region, the region in which the BPCB device is fabricated in, however at the expense of performance, in terms of the frequency response, (Ft), or the device.
This invention will describe a BPCB, bipolar device, in which polysilicon field plates are placed on field oxide regions, which results in a potential shift, which in turn results in a reduction in surface electric field, thus improving, or increasing, the BVceo parameter to a values greater than 50 volts. In addition the use of the polysilicon field plates, presenting improved breakdown characteristics, thus allows higher N well concentrations to be tolerated, thus allowing higher Ft to be realized. The BPCB bipolar device is easily integrated into a conventional CMOS fabrication process, sharing many process steps, thus reducing the complexity of the BiCMOS integrated fabrication procedure. Prior art, such as Contiero et al, in U.S. Pat. No. 5,589,405, as well as Whitney, in U.S. Pat. No. 5,750,414, describe field plates overlying CMOS devices, however not the configuration, or process sequence, used in this novel application, where the polysilicon field plates are placed on field oxide regions, where the field oxide region is located between a base and collector region, resulting in enhanced breakdown characteristics of a BPCB bipolar device.
SUMMARY OF THE INVENTION
It is an object of this invention to fabricate a buried layer pinched collector bipolar, (BPCB), device, and an a CMOS device, using an integrated fabrication sequence.
It is another object of this invention to increase the collector—base breakdown voltage, of the BPCB, bipolar device, via use of polysilicon field plates, placed on field oxide regions, and located overlying a region between the collector and base regions, of the BPCB device.
It is still another object of this invention to increase the Ft of the BPCB bipolar device via use of increased N well dopant concentration.
In accordance with the present invention, a buried layer pinched collector, (BPCB), bipolar device, fabricated simultaneously with CMOS devices, featuring polysilicon field plates, located on field oxide regions, that in turn are located between a base and a collector region of the BPCB device, and used to improve collector - emitter breakdown voltage of the device, is described. After formation of an P type, buried layer region, in a semiconductor substrate, a thick, P type, epitaxial silicon layer is deposited, followed by the creation of an N well region, in an area of the P type, epitaxial silicon layer, to be used for a NPN, BPCB bipolar device. Field oxide regions are next formed followed by the formation of polysilicon field plates, located overlying the field oxide regions. A P type, base region is next formed in an area of the N well region, located between field oxide regions, followed by the creation of an N type, emitter region, formed in a top portion of the P type, base region, and the creation of N type, collector regions, formed in a portion the N well region, adjacent to the outside edges of the field oxide region
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Goud, C.B., Bhat, K.N.; Analysis and Optimal Design of Semi-Insulator Passivated High-Voltage Field Plate Structures and Comparison with dielectric Passivated Structures, IEEE Transactions on Electron Devices, vol. 41, No. 10 Oct. 1994, pp. 1856-1865.
Hwang Jei-Feng
Jiang Jyh-Min
Liou Ruey-Hsin
Tsai Jun-Lin
Ackerman Stephen B.
Lattin Christopher
Niebling John F.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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