Use of poly resistor implant to dope poly gates

Details Use of poly resistor implant to dope poly gates Use of poly resistor implant to dope poly gates

2008-11-05

2010-12-07

Richards, N Drew (Department: 2895)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

C438S138000, C438S152000, C438S207000, C438S230000, C438S238000, C438S299000, C438S382000, C257SE21637

Reexamination Certificate

active

07846783

ABSTRACT:
A process of fabricating an IC is disclosed in which a polysilicon resistor and a gate region of an MOS transistor are implanted concurrently. The concurrent implantation may be used to reduce steps in the fabrication sequence of the IC. The concurrent implantation may also be used to provide another species of transistor in the IC with enhanced performance. Narrow PMOS transistor gates may be implanted concurrently with p-type polysilicon resistors to increase on-state drive current. PMOS transistor gates over thick gate dielectrics may be implanted concurrently with p-type polysilicon resistors to reduce gate depletion. NMOS transistor gates may be implanted concurrently with n-type polysilicon resistors to reduce gate depletion, and may be implanted concurrently with p-type polysilicon resistors to provide high threshold NMOS transistors in the IC.

REFERENCES:
patent: 5506158 (1996-04-01), Eklund
patent: 6001677 (1999-12-01), Shimizu

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