Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
1999-04-12
2001-02-20
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
C430S005000
Reexamination Certificate
active
06191036
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the manufacture of high performance semiconductor devices. More specifically, this invention relates to a method of monitoring an etch monitor structure that would predict the etch quality of the semiconductor manufacturing process. Even more specifically, this invention relates to a method of using an array of photo focus exposure matrices to predict the etch quality of the semiconductor manufacturing process.
2. Discussion of the Related Art
In order to remain competitive, a semiconductor manufacturer must continuously increase the performance of the semiconductor integrated circuits being manufactured and at the same time, reduce the cost of the semiconductor integrated circuits. Part of the increase in performance and the reduction in cost of the semiconductor integrated circuits is accomplished by shrinking the device dimensions and by increasing the number of circuits per unit area on an integrated circuit chip. Another part of reducing the cost of a semiconductor chip is to increase the yield. As is known in the semiconductor manufacturing art, the yield of chips (also known as die) from each wafer is not 100% because of defects incurred during the manufacturing process. The number of good chips obtained from a wafer determines the yield. As can be appreciated, chips that must be discarded because of a defect increases the cost of the remaining usable chips.
A single semiconductor chip can require numerous process steps such as oxidation, etching, metallization and wet chemical cleaning. Some of these process steps involve placing the wafer on which the semiconductor chips are being manufactured into different tools during the manufacturing process. The optimization of each of these process steps requires an understanding of a variety of chemical reactions and physical processes in order to produce high performance, high yield circuits. The ability to view and characterize the surface and interface layers of a semiconductor chip in terms of their morphology, chemical composition and distribution is an invaluable aid to those involved in research and development, process, problem solving, and failure analysis of integrated circuits.
Modern very large-scale monolithic silicon devices require many millions of transistors for high performance operation. These millions of transistors must all maintain full functionality for the device to operate properly. This requires that every transistor must not only be formed without error but also that they retain the ability to be interconnected to virtually any other transistor on the device. This interconnectivity is accomplished through multiple vias through multiple interlayer dielectrics. The typical method of forming vias is to deposit a layer of photoresist on a layer of interlayer dielectric material, exposing the photoresist, and developing the photoresist. This series of processes exposes portions of the metal layer underlying the interlayer dielectric on which the vias are to be formed.
One inherent problem with this method of forming vias is the difficulty of discerning whether all of the vias are open to the bottom of the interlayer dielectric during the etch process. In an environment in which even one partially etched via can degrade device performance or even cause the device to fail (kill the device) it is critical to have a reliable method of determining when the true end-of-etch has been reached. Due to natural variations in process, including variations in etch rate, variations in the thickness of the interlayer dielectric, a pilot wafer is usually processed and inspected prior to committing the rest of the wafers in the manufacturing lot. The inspection of the pilot wafer is necessarily done in a SEM (scanning electron microscope) and is a time consuming process preventing the further processing of the remaining wafers in the lot. The selection of the pilot wafer is a random sample, which yields inspector dependent subjective or qualitative results.
There currently exists an array of photo focus exposure matrices (FEM) that aid in monitoring the focus, exposure and development process integrity. The matrices are a sequence of via dot array test patterns migrating down in size from about double the minimum dimension to half the minimum dimension at 0.05 &mgr;m decrements. These patterns provides the DI (develop inspect) inspector a tool to quickly determine whether the current process is defining the mask to the wafer properly. These patterns are also available to the A/E (after etch inspect) inspector and the FI (final inspect) inspector.
The inventors have extensively studied the patterns in relation to the overall etch integrity and have determined that there is a correlation for each increment of via dots to the overall etch integrity. Due to the aspect ratio etch dependency phenomenon, the next smaller dimension of via dots etches slower than the previous dimension, resulting in an incomplete etch of the via to the bottom of the layer of the interlayer dielectric. In lithography, the dots take longer to expose and open to the bottom of the layer of the interlayer dielectric. The inventors have discovered that closed and incomplete vias are usually accompanied with shallow or missing via dots in the next incremental matrix in the array of matrices in the FEM. At the pre-etch level, when the via dots have low contrast, the vias do not open to the surface of the underlying metal layer. The same phenomenon happens at the post resist strip level. This “forward looking” technique can also apply to the pre-etch level where two increments of complete matrix of dots will be used without stripping the photoresist mask. This corresponds to one decrement from after etch to post strip.
Therefore, what is needed is an etch monitor structure that can be inspected optically and evaluated quantitatively to predict etch efficacy.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are attained by a method of predicting etch efficacy of vias in a semiconductor manufacturing process by using a photo focus exposure matrix (FEM) array as a via etch monitor.
In accordance with an aspect of the invention, the FEM array is inspected, a matrix in the array having incomplete via dots is identified and determining the etch efficacy of a via dimension by decrementing two sizes from the matrix that has incomplete via dots.
In accordance with another aspect of the invention, each of the matrices have a different size starting with a size approximately double the minimum dimension of vias in the semiconductor wafer and decrementing by approximately 0.05 &mgr;m to a size approximately half the minimum dimension.
In accordance with still another aspect of the invention, the FEM array is electronically inspected and the inspection data is sent to an electronic interface.
In accordance with another aspect of the invention, the etch recipe for the subsequent etch process is adjusted using the inspection data from the electronic interface.
The method of the invention is an accurate method of predicting the efficacy of vias that will be formed in the wafer and for avoiding the necessity for reworking the wafer lot when a defective photoresist development process has been detected during the inspection of the FEM.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
REFERENCE
Rangarajan Bharath
Steffan Paul J.
Yu Allen S.
Advanced Micro Devices , Inc.
Chen Kin-Cha
Kunemund Robert
Nelson H. Donald
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