Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-08-25
2002-07-02
Christianson, Keith (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S108000, C438S613000, C438S614000
Reexamination Certificate
active
06413862
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and a method for forming a conductive polymer bump on a substrate, such as a flip-chip type semiconductor die, a silicon wafer, a printed circuit board, or other substrate (hereinafter referred to generally as a “substrate”). More particularly, the present invention relates to forming a substrate having a palladium metal layer over each contact point of the substrate and forming a flexible conductive polymer bump on each contact point. The present invention also relates to assemblies and methods of connecting one or more of these substrates together or to another substrate.
2. State of the Art
A flip chip is a semiconductor chip or die that has bumped terminations spaced around an active surface of the die and is intended for face-to-face attachment to a substrate or another semiconductor die. The bumped terminations of the flip chips are usually a “Ball Grid Array” (“BGA”) configuration wherein an array of minute solder balls is disposed on an attachment surface of a semiconductor die, or a “Slightly Larger than Integrated Circuit Carrier” (“SLICC”) configuration wherein an array of minute solder balls is disposed on an attachment surface of a semiconductor die similar to a BGA, but having a smaller solder ball pitch and diameter than a BGA.
The attachment of a flip chip to a substrate or another semiconductor involves aligning the solder balls on the flip chip with a plurality of contact points (configured to be a mirror image of the solder ball arrangement on the flip chip) on a facing surface of the substrate. A plurality of solder balls may also be formed on the facing surface of the substrate at the contact points. A quantity of liquid flux is often applied to the face of the chip and/or substrate, and the chip and substrate are subjected to elevated temperatures to effect reflowing or soldering of the solder balls on the chip and/or corresponding solder balls on the substrate. This connection technology is also referred to as “flip chip attachment” or “C4—Controlled Collapse Chip Connection.”
High performance microelectronic devices generally comprise a number of flip chips attached to a substrate or printed circuit board (“PCB”) for electrical interconnection to other microelectronic devices. For example, a very large scale integration (“VLSI”) chip may be electrically connected to a substrate, printed circuit board, or other next level packaging substrate.
Flip chip attachment requires the formation of contact terminals on flip chip contact sites, each consisting of a metal pad with a solder ball disposed thereon. Flip chip attachment also requires the formation of solder joinable sites (“bond pads”) on the metal conductors of the substrate or PCB which are a mirror-image of the solder ball arrangement on the flip chip. The bond pads on the substrate are usually surrounded by non-solderable barriers so that when the solder of the bond pads and of the chip contact sites melts and merges (“reflow”), the surface tension holds the semiconductor chip by solder columns, as if suspended above the substrate. After cooling, the chip is essentially welded face-down by these very small, closely spaced solder column interconnections.
It is also known in the art that conductive polymers or resins can be utilized in lieu of solder balls. U.S. Pat. No. 5,258,577 issued Nov. 2, 1993 to Clements relates to a substrate and a semiconductor die with a discontinuous passivation layer. The discontinuities result in vias between the contact points of the substrate and the semiconductor die. A resin with spaced conductive metal particles suspended therein is disposed within the vias to achieve electrical contact between the substrate and the semiconductor die. U.S. Pat. No. 5,468,681 issued Nov. 21, 1995 to Pasch relates to interconnecting conductive substrates using an interposer having conductive plastic filled vias. U.S. Pat. No. 5,478,007 issued Dec. 26, 1995 to Marrs relates to using conductive epoxy as a bond pad structure on a substrate for receiving a coined ball bond on a die to achieve electrical communication between the die and the substrate.
Such flip chip and substrate attachments (collectively “electronic packages”) are generally comprised of dissimilar materials that expand at different rates on heating. The most severe stress is due to the inherently large thermal coefficient of expansion (“TCE”) mismatch between the plastic and the metal. These electronic packages are subject to two types of heat exposures: process cycles, which are often high in temperature but few in number; and operation cycles, which are numerous but less extreme. If either the flip chip(s) or substrate(s) are unable to repeatedly bear their share of the system thermal mismatch, the electronic package will fracture, which destroys the functionality of the electronic package.
As an electronic package dissipates heat to its surroundings during operation, or as the ambient system temperature changes, differential thermal expansions cause stresses to be generated in the interconnection structures (e.g., solder ball bonds) between the semiconductor die and the substrate. These stresses produce instantaneous elastic and, most often, plastic strain, as well as time-dependent (plastic and anelastic) strains in the joint, especially within its weakest segment. Thus, the TCE mismatch between chip and substrate will cause a shear displacement to be applied on each terminal which can fracture the solder connection.
The problem with TCE mismatch becomes evident during the process of burn-in. Burn-in is the process of electrically stressing a device, usually at an elevated temperature and voltage environment, for an adequate period of time to cause failure of marginal devices. When a chip, such as a flip chip, breaks free from the substrate due to TCE mismatch, defective bonds, or the like, the chip must be reattached and the burn-in process reinitiated. This requires considerable time and effort which results in increased production costs. Alternately, if the chip has been underfilled and subsequently breaks free during burn-in, the chip is not reworkable and must be discarded.
The problems with TCE mismatch are also applicable to connections made with conductive polymers or resins, because after curing the polymers or resins become substantially rigid. The rigid connections are equally susceptible to breakage due to TCE mismatch.
FIGS. 1
a-
1
e
show a contemporary, prior art method of forming a conductive bump arrangement on a substrate. First, as shown in
FIG. 1
a,
a passivation film
102
, such as at least one layer of SiO
2
film, Si
3
N
4
film, or the like, is formed over a face surface
104
of a semiconductor wafer
100
which has a conductive electrode
106
, usually an aluminum electrode. The passivation film
102
is selectively etched to expose the conductive electrode
106
.
FIG. 1
b
shows a metal layer
108
applied over a face surface
110
of the passivation film
102
by deposition or sputtering. A second layer of etch resist film
112
is applied to a face surface
114
of the metal layer
108
. The second etch resist film
112
is masked, exposed, and stripped to expose a portion of the metal layer
108
corresponding to the conductive electrode
106
, as shown in
FIG. 1
c
. A solder bump
116
(generally an alloy of lead and tin) is then formed on the exposed portion of the metal layer
108
, as shown in
FIG. 1
d
, by any known industry technique, such as stenciling, screen printing, electroplating, electrolysis, or the like. The second etch resist film
112
is removed and the metal layer
108
is removed using the solder bump
116
as a mask to form the structure shown in
FIG. 1
e.
This conventional bump formation method has drawbacks. The most obvious being the large number of process steps required which results in high manufacturing costs.
U.S. Pat. No. 4,970,571 issued Nov. 13, 1990 to Yamakawa et al. (the '571 patent) relates to a bump formation method which addresses the prob
Akram Salman
Farnworth Warren M.
Christianson Keith
Huynh Yennhu B.
Micro)n Technology, Inc.
TraskBritt
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