Use of multiple etching steps to reduce lateral etch undercut

Details Use of multiple etching steps to reduce lateral etch undercut Use of multiple etching steps to reduce lateral etch undercut

2006-07-04

2006-07-04

Luu, Chuong A. (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S736000, C438S671000, C438S401000, C438S448000

Reexamination Certificate

active

07071115

ABSTRACT:
In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

REFERENCES:
patent: 4981550 (1991-01-01), Huttemann et al.
patent: 5604156 (1997-02-01), Chung et al.
patent: 5893744 (1999-04-01), Wang
patent: 6355524 (2002-03-01), Tuan et al.
patent: 6403417 (2002-06-01), Chien et al.
patent: 6451708 (2002-09-01), Ha
patent: 6541324 (2003-04-01), Wang
patent: 2003/0067806 (2003-04-01), Tuan
Naruke, K.; Yamada, S.; Obi, E.; Taguchi, S.; and Wada, M. “A New Flash-Erase EEPROM Cell with A Sidewall Select-Gate On Its Source Side,” 1989 IEEE, pp. 604-606.
Wu, A. T.; Chan T. Y.; Ko, P.K.; and Hu, C. “A Novel High-Speed, 5-Volt Programming EPROM Structure With Source-Side Injection,” 1986 IEEE, 584-587.
Mizutani, Yoshihisa; and Makita, Koji “A New EPROM Cell With A Sidewall Floating Gate Fro High-Density and High Performance Device,” 1985 IEEE, 635-638.
Ma, Y.; Pang, C.S.; Pathak, J.; Tsao, S.C.; Chang, C.F.; Yamauchi, Y.; Yoshimi, M. “A Novel High Density Contactless Flash Memory Array Using Split-Gate Source-Side-Injection Cell for 5V-Only Applications,” 1994 Symposium on VLSI Technology Digest of Technical Papers, pp. 49-50.
Mih, Rebecca et al. “0.18um Modular Triple Self-Aligned Embedded Split-Gate Flash Memory,” 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 120-121.
K. Naruke et al., “A New Flash-Erase EEPROM Cell with a Sidewall Select-Gate on Its Source Side”, IEDM Technical Digest 1989, pp. 603-606.
U.S. Appl. No. 10/402,698, filed Mar. 28, 2003, Chung et al.
R. Mih et al., “0.18um Modular Triple Self-Aligned Embedded Split-Gate Flash Memory”, 2000 Symposium on VLSI Technology, Digest of Technical Papers, pp. 120-121.

Affiliated with

Also associated with

Rating

Use of multiple etching steps to reduce lateral etch undercut does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Use of multiple etching steps to reduce lateral etch undercut, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Use of multiple etching steps to reduce lateral etch undercut will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3594808