Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-02-25
2001-04-24
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S423000, C438S658000
Reexamination Certificate
active
06221768
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to integrated circuits and, in particular, to a method of memory device fabrication which improves memory cell reliability and manufacturability by preventing formation of poly stringers caused by an oxide-nitride-oxide (ONO) fence.
BACKGROUND OF THE INVENTION
Semiconductor devices typically include multiple individual components formed on or within a substrate. Such devices often comprise a high density section and a low density section. For example, as illustrated in prior art
FIG. 1
, a memory device such as a flash memory
10
comprises one or more high density core regions
12
and a low density peripheral portion
14
on a single substrate
16
. The high density core regions
12
typically consist of at least one MxN array of individually addressable, substantially identical memory cells and the low density peripheral portion
14
typically includes input/output (I/O) circuitry and circuitry for selectively addressing the individual cells (such as decoders for connecting the source, gate and drain of selected cells to predetermined voltages or impedances to effect designated operations of the cell such as programming, reading or erasing).
The memory cells within the core portion
12
are coupled together in a circuit configuration, such as that illustrated in prior art FIG.
2
. Each memory cell
20
has a drain
22
, a source
24
and a stacked gate
26
. Each stacked gate
26
is coupled to a word line (WL
0
, WL
1
, . . . , WL
N
) while each drain
22
is coupled to a bit line (BL
0
, BL
1
, . . . , BL
N
). Lastly, each source
24
is coupled to a common source line CS. Using peripheral decoder and control circuitry, each memory cell
20
can be addressed for programming, reading or erasing functions.
Prior art
FIG. 3
represents a fragmentary cross-sectional diagram of a typical memory cell
20
in the core region
12
of prior art
FIGS. 1 and 2
. Such a memory cell
20
typically includes the source
24
, the drain
22
and a channel
28
in a substrate
30
; and the stacked gate structure
26
overlying the channel
28
. The stacked gate
26
includes a thin gate dielectric layer
32
(commonly referred to as the tunnel oxide) formed on the surface of the substrate
30
. The tunnel oxide layer
32
coats the top surface of the silicon substrate
30
and serves to support an array of different layers directly over the channel
28
. The stacked gate
26
includes a lower most or first film layer
38
, such as doped polycrystalline silicon (polysilicon or poly I) layer which serves as a floating gate
38
that overlies the tunnel oxide
32
. On top of the poly I layer
38
is an interpoly dielectric layer
40
. The interpoly dielectric layer
40
is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer, or an alternative can be any other dielectric layer such as tantalum pentoxide. Finally, the stacked gate
26
includes an upper or second polysilicon layer (poly II)
44
which serves as a polysilicon control gate overlying the ONO layer
40
. The control gates
44
of the respective cells
20
that are formed in a given row share a common word line (WL) associated with the row of cells (see, e.g., prior art FIG.
2
). In addition, as highlighted above, the drain regions
22
of the respective cells in a vertical column are connected together by a conductive bit line (BL). The channel
28
of the cell
20
conducts current between the source
24
and the drain
22
in accordance with an electric field developed in the channel
28
by the stacked gate structure
26
.
According to conventional operation, the memory cell
20
(e.g., flash memory cell) operates in the following manner. The memory cell
20
is programmed by applying a relatively high voltage V
G
(e.g., approximately 12 volts) to the control gate
38
and a moderately high voltage V
D
(e.g., approximately 9 volts) to the drain
22
in order to produce “hot” (high energy) electrons in the channel
28
near the drain
22
. The hot electrons accelerate across the tunnel oxide
32
and into the floating gate
34
and become trapped in the floating gate
38
because the floating gate
38
is surrounded by insulators (the interpoly dielectric
40
and the tunnel oxide
32
). As a result of the trapped electrons, a threshold voltage (V
T
) of the memory cell
20
increases by about 3 to 5 volts. This change in the threshold voltage (and thereby the channel conductance) of the memory cell
20
created by the trapped electrons is what causes the memory cell
20
to be programmed.
To read the memory cell
20
, a predetermined voltage V
G
that is greater than the threshold voltage of an unprogrammed memory cell, but less than the threshold voltage of a programmed memory cell, is applied to the control gate
44
. If the memory cell
20
conducts, then the memory cell
20
has not been programmed (the memory cell
20
is therefore at a first logic state, e.g., a zero “
0
”). Likewise, if the memory cell
20
does not conduct, then the memory cell
20
has been programmed (the memory cell
20
is therefore at a second logic state, e.g., a one “
1
”). Thus, each memory cell
20
may be read in order to determine whether it has been programmed (and therefore identify its logic state).
In order to erase the memory cell
20
, a relatively high voltage V
S
(e.g., approximately 12 volts) is applied to the source
24
and the control gate
44
is held at a ground potential (V
G
=0), while the drain
22
is allowed to float. Under these conditions, a strong electric field is developed across the tunnel oxide
32
between the floating gate
38
and the source region
24
. The electrons that are trapped in the floating gate
38
flow toward and cluster at the portion of the floating gate
38
overlying the source region
24
and are extracted from the floating gate
38
and into the source region
22
by way of Fowler-Nordheim tunneling through the tunnel oxide
32
. Consequently, as the electrons are removed from the floating gate
38
, the memory cell
20
is erased.
Having described a structural arrangement of the memory cell
20
, attention is now brought to fabrication of the memory device
10
.
FIG. 4
illustrates an overall arrangement of the memory device
10
at an early stage of formation. A substrate
30
is shown which comprises regions of thick oxide (field oxide)
34
and thin oxide (tunnel oxide)
32
. The field oxide
34
provides for electrically insulating transistors from one and other. A poly I layer
38
has been laid down over the substrate
30
, and sections of the poly I layer
38
have been patterned and masked such that an unmasked portion
42
is etched away using convention photolithographic techniques so as to form a series of poly I layer rows
38
.
FIG. 5
illustrates an ONO layer
40
laid down over the poly I layer rows
38
and the partially exposed field oxide regions
34
between the rows of poly I layer
38
. More particularly, since sections of the poly I layer
38
have been etched away, gaps
42
exist between the rows of poly I layer
38
such that sidewalls of the poly I layer rows become coated with the ONO layer material
40
as it is being deposited. The etching step of the poly I layer
38
results in the ONO layer
40
being deposited thereon to be non-uniform in step height. More specifically, since there are gaps
42
between the rows of poly I layer
38
, and since the ONO layer conforms to the topography on which it is deposited, the ONO that lies along the sidewalls of the etched poly I lines is significantly thicker that the ONO on top of either the flat portion of the poly I or the flat portion of the field oxide. It is to be appreciated that the thickness of the ONO layer
40
in the figures is shown to be relatively the same as the other layers for ease of understanding, however, the ONO layer
40
is actually very thin relative to the poly I layer
38
and poly II layer
44
(
FIG. 6
a
).
After application of the ONO layer
40
Advanced Micro Devices , Inc.
Amin, Eschweiler & Turocy, LLP
Elms Richard
Wilson Christian D.
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