Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-03-13
2003-11-04
Booth, Richard (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S261000, C438S785000, C438S954000
Reexamination Certificate
active
06642573
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a process for preparation of a semiconductor device including forming a modified ONO structure. The modified ONO structure comprises a high-K dielectric material.
BACKGROUND ART
Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Product development efforts in EEPROM device technology have focused on increasing the programming speed, lowering programming and reading voltages, increasing data retention time, reducing cell erasure times and reducing cell dimensions. One important dielectric material for the fabrication of the EEPROM is an oxide-nitride-oxide (ONO) structure. One EEPROM device that utilizes the ONO structure is a silicon-oxide-nitride-oxide-silicon (SONOS) type cell. A second EEPROM device that utilizes the ONO structure is a floating gate flash memory device, in which the ONO structure is formed over the floating gate, typically a polysilicon floating gate.
In SONOS devices, during programming, electrical charge is transferred from the substrate to the silicon nitride layer in the ONO structure. Voltages are applied to the gate and drain creating vertical and lateral electric fields, which accelerate the electrons along the length of the channel. As the electrons move along the channel, some of the electrons gain sufficient energy to jump over the potential barrier of the bottom silicon dioxide layer and become trapped in the silicon nitride layer. Electrons are trapped near the drain region because the electric fields are the strongest near the drain. Reversing the potentials applied to the source and drain will cause electrons to travel along the channel in the opposite direction and be injected into the silicon nitride layer near the source region. Because silicon nitride is not electrically conductive, the charge introduced into the silicon nitride layer tends to remain localized. Accordingly, depending upon the application of voltage potentials, electrical charge can be stored in discrete regions within a single continuous silicon nitride layer.
Non-volatile memory designers have taken advantage of the localized nature of electron storage within a silicon nitride layer and have designed memory circuits that utilize two regions of stored charge within an ONO layer. This type of non-volatile memory device is known as a two-bit EEPROM, which is available under the trademark MIRRORBIT™ from Advanced Micro Devices, Inc., Sunnyvale, Calif. The MIRRORBIT™ two-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left and right bit is stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell. Programming methods are then used that enable two bits to be programmed and read simultaneously. The two-bits of the memory cell can be individually erased by applying suitable erase voltages to the gate and to either the source or drain regions.
As device dimensions continue to be reduced, the electrical thickness of the ONO layer must be reduced accordingly. Previously, this has been accomplished by scaling down the physical thickness of the ONO layer. However, as the ONO layer is made physically thinner, leakage current through the ONO layer may increase, and the charge trapping ability of the nitride layer may be reduced, which limits the scaling down of the total physical thickness of the ONO layer.
A floating gate flash device includes a floating gate electrode upon which electrical charge is stored. The floating gate electrode is formed on a tunnel oxide layer which overlies a channel region residing between the source and drain regions in a semiconductor substrate. The floating gate electrode together with the source and drain regions form an enhancement transistor. Typically, the floating gate electrode may be formed of polysilicon.
In a floating gate flash device, electrons are transferred to the floating gate electrode through a dielectric layer overlying the channel region of the enhancement transistor. The electron transfer is initiated by either hot electron injection, or by Fowler-Nordheim tunneling. In either electron transfer mechanism, a voltage potential is applied to the floating gate electrode by an overlying control gate electrode. The control gate electrode is capacitively coupled to the floating gate electrode, such that a voltage applied on the control gate electrode is coupled to the floating gate electrode. The floating gate flash device is programmed by applying a high positive voltage to the control gate electrode, and a lower positive voltage to the drain region, which transfers electrons from the channel region to the floating gate electrode.
The control gate electrode is separated from the floating gate electrode by an interpoly dielectric layer, typically an oxide-nitride-oxide stack, i.e., an ONO structure or layer. However, as device dimensions continue to be reduced, the electrical thickness of the interpoly dielectric layer between the control gate electrode and the floating gate electrode must be reduced accordingly. Previously, this has been accomplished by scaling down the physical thickness of the ONO layer. However, as the ONO layer is made physically thinner, leakage current through the ONO layer may increase, which limits the scaling down of the total physical thickness of the ONO layer.
Some of the improvements in devices can be addressed through development of materials and processes for fabricating the ONO layer. Recently, development efforts have focused on novel processes and materials for use in fabrication of the ONO layer. While the recent advances in EEPROM technology have enabled memory designers to double the memory capacity of EEPROM arrays using two-bit data storage, numerous challenges exist in the fabrication of material layers within these devices. In particular, the ONO layer must be carefully fabricated to avoid an increase in the leakage current. Accordingly, advances in ONO fabrication and materials technology are needed to ensure proper charge isolation in ONO structures used in MIRRORBIT™ two-bit EEPROM devices and in floating gate flash devices.
DISCLOSURE OF INVENTION
In one embodiment, the present invention relates to a semiconductor device including a modified ONO structure, wherein the modified ONO structure comprises a bottom dielectric material layer, a silicon nitride layer on the bottom dielectric material layer, and a top dielectric material layer on the silicon nitride layer, in which at least one of the bottom dielectric material layer and the top dielectric material layer comprises a composite dielectric material, and in which the composite dielectric material comprises elements of at least one mid-K or high-K dielectric material.
In another embodiment, the present invention relates to a non-volatile memory cell including a) a substrate comprising a source region, a drain region, and a channel region positioned therebetween; b) a floating gate positioned above the channel region and separated from the channel region by a tunnel dielectric material layer; and c) a control gate positioned above the floating gate and separated from the floating gate by an interpoly dielectric layer, the interpoly dielectric layer comprising a bottom dielectric material layer adjacent to the floating gate, a top dielectric material adjacent to the control gate, and a center la
Cheung Fred T. K.
Halliyal Arvind
Ramsbey Mark T.
Randolph Mark W.
Zhang Wei
Advanced Micro Devices , Inc.
Booth Richard
Renner , Otto, Boisselle & Sklar, LLP
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