Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-10-08
2004-09-07
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06789245
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to electronic component design and, more particularly, to alteration of signal speed on a network signal wire in order to balance skew in the network.
2. Description of Related Art
Currently, most mainstream electronic components and systems, such as microprocessors, are synchronous systems employing one or more system clocks that act as the driving force or “heart” of the electronic system. As a result, more often than not, it is critical that a given system clock signal arrive at various points in the system at nearly the same time. As discussed below, this situation can create significant complications in microprocessor design.
FIG. 1
illustrates a portion of a length of signal wire
100
including, from left to right, in the direction shown by arrow
120
, points
102
,
104
and
106
. As is well known, the physics of conductors and wave propagation dictate two precepts: first, the absolute speed limit for any signal moving from point
102
to points
104
or
106
is the speed of light; second, since wire
100
is typically a metallic conductor, with an inherent resistance, a signal propagating in wire
100
actually travels at a speed significantly less than the speed of light.
As a result of these physical limitations on the speed at which a signal can propagate through wire
100
, it follows that the greater the distance between two points on/in wire
100
, the longer it takes the signal to reach the point. Consequently, a signal traveling from point
102
, in the direction shown by arrow
120
, will take less time to reach point
104
, i.e., travel distance
108
, than it will take to reach point
106
, i.e., travel distance
108
and distance
110
; and thus, there is a time delay between when the signal reaches point
104
and when it reaches point
106
. In addition, as can be seen from the discussion above, as long as wire
100
has a reasonably consistent composition and the wire lies on the same metal layer, the time delay is typically proportional to the distance traveled, i.e., twice the distance results in approximately four times the delay.
Typically there are numerous circuit components, located at different distances from the system clock(s) that must receive the clock signal at the same time over interconnecting signal wires. Given the discussion above with respect to
FIG. 1
, it can be understood that the problem of ensuring a given clock signal is received at a first point and at other variously distanced points, nearly simultaneously, is significant.
One prior art method used to ensure the receipt of a clock signal at the same time at variously distanced points, was to introduce a time delay on the shorter signal paths by forming serpentine signal paths. The introduction of a time delay, also called simply a “delay”, between when one point receives a signal and when a second point, that should receive the signal at the same time, actually receives the signal, is known as skew. When the signal is a clock signal, then it is known as clock skew. Serpentining the signal wire between close points increased the actual length of the signal path over the original distance between the points, and delayed the signal so that the signal arrived at the more distant point at the same time as the close points. Conventionally, serpentining a signal wire involves routing the signal wire in vertical and horizontal directions on the same microprocessor layer using wire jogs.
Although a select signal, such as a clock signal, may need to be delayed in route to a particular component in order to balance skew in the network, optimizing the signal speed in the device is still important in order for the device to remain competitive in the market. To aid in maintaining the integrity and speed of a signal carried on a signal wire, shielding wires are often routed to each side of the signal wire to reduce the effects of electrical noise on the signal wire from other components and signals in the device that can disrupt and delay a signal on the signal wire.
Conventionally, shielding wires are offset a predetermined offset distance from the signal wire to minimize interactions between the shielding wires and the signal wire that could disrupt or delay a signal. Particularly, the shielding wires are positioned at an offset distance to minimize interactions, such as capacitive coupling, between the shielding wires and the signal wire which can result in increased noise and delay on the signal wire. When a signal wire has a serpentine path, typically, the shielding wires follow the serpentine pattern, as needed, at the specified offset distance from the signal wire.
FIG. 2
illustrates a microprocessor clock network having two signal paths issuing from a clock signal source, in which the shorter signal path has a time delay introduced into it by serpentining the signal path. In
FIG. 2
, microprocessor layer
210
includes clock source
212
that sends clock signals over branched signal wire
220
to two components
214
and
216
. Component
214
is located a distance D1 from clock source
212
directly off of signal wire
220
that is shielded by shielding wires
222
and
224
. Component
216
, however, is located a shorter distance D2 from clock source
212
indirectly off of signal wire
220
, namely, off of a portion of signal wire
220
and branch signal wires
230
and
240
, and shielded by shielding wires
232
and
234
and shielding wires
242
and
244
, respectively. As distance D1 is larger than distance D2, component
214
is farther from clock source
212
than component
216
resulting in a clock skew, e.g., a signal will take longer to reach component
214
than component
216
. To ensure the clock signal arrives at both components
214
and
216
, nearly simultaneously, signal wire branch
240
is serpentined to increase the actual distance of the signal path to component
216
. Thus, the actual signal path length along signal wire branch
240
is longer so as to delay the transit time of a signal to component
216
and balance the clock skew in the network.
While this technique enables the clock signal to arrive at different components, nearly simultaneously, the more complex signal and shielding wire routings can increase the design and process complexity as well as processing time and costs.
SUMMARY OF THE INVENTION
According to the principles of this invention, methods and devices for using the coupling capacitance of shielding wires to balance skew in a network are described.
According to one embodiment of the present invention, a method for balancing skew in a network includes: designating a first signal wire in a network, the first signal wire communicatively coupling a sending component with a first receiving component, the first receiving component being located along the first signal wire a first distance from the sending component, the first signal wire carrying a signal sent from the sending component to the first receiving component; designating a second signal wire in the network, the second signal wire communicatively coupling the sending component with a second receiving component, the second receiving component being located along the second signal wire a second distance from the sending component, the second distance being less than the first distance, the second signal wire carrying the signal sent from the sending component to the second receiving component; positioning first and second shielding wires oppositely adjacent the first signal wire at a first offset distance, the first and second shielding wires exerting a first capacitive coupling effect on the first signal wire; positioning third and fourth shielding wires oppositely adjacent the second signal wire at a second offset distance, the third and fourth shielding wires exerting a second capacitive coupling effect on the second signal wire that is greater than the first capacitive effect on the first signal wire such that the signal arrives at the first and second receiving components at nea
Hogenmiller David
Hojat Shervin
Sharma Harsh
Dimyan Magid Y.
Gunnison McKay & Hodgson, L.L.P.
Norris Lisa A.
Sun Microsystems Inc.
Thompson A. M.
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