Use of conductive electrolessly deposited etch stop layers,...

Details Use of conductive electrolessly deposited etch stop layers,... Use of conductive electrolessly deposited etch stop layers,...

2006-03-07

2006-03-07

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S627000

Reexamination Certificate

active

07008872

ABSTRACT:
Multiple level interconnect structures and methods for fabricating the interconnect structures are disclosed. The interconnect structures may contain an interconnect line, an electrolessly deposited metal layer formed over the interconnect line, a via formed over the metal layer, and a second interconnect line formed over the via. Often the metal layer contains a cobalt or nickel alloy and provides an etch stop layer for formation of an opening corresponding to the via. The metal layer may provide protection to the underlying interconnect line and may replace a traditional protective dielectric layer. The metal layer is conductive, rather than dielectric, and provides a shunt for passage of electrical current between the via and the interconnect line. Similar metal layers may also be used within the interconnect structures as via liner layers and via plugs.

REFERENCES:
patent: 4574094 (1986-03-01), DeLuca et al.
patent: 4574095 (1986-03-01), Baum et al.
patent: 4789648 (1988-12-01), Chow et al.
patent: 4894260 (1990-01-01), Kumasaka et al.
patent: 4985750 (1991-01-01), Hoshino
patent: 5151168 (1992-09-01), Gilton et al.
patent: 5240497 (1993-08-01), Shacham et al.
patent: 5612254 (1997-03-01), Mu et al.
patent: 5619072 (1997-04-01), Mehta
patent: 5674787 (1997-10-01), Zhao et al.
patent: 5695810 (1997-12-01), Dubin et al.
patent: 5739579 (1998-04-01), Chiang et al.
patent: 5891513 (1999-04-01), Dubin et al.
patent: 6100184 (2000-08-01), Zhao et al.
patent: 6153935 (2000-11-01), Edelstein et al.
patent: 6169024 (2001-01-01), Hussein
patent: 6174812 (2001-01-01), Hsiung et al.
patent: 6197688 (2001-03-01), Simpson
patent: 6207556 (2001-03-01), Hsu
patent: 6258707 (2001-07-01), Uzoh
patent: 6310019 (2001-10-01), Kakizawa et al.
patent: 6316359 (2001-11-01), Simpson
patent: 6342733 (2002-01-01), Hu et al.
patent: 6350687 (2002-02-01), Avanzino et al.
patent: 6358832 (2002-03-01), Edelstein et al.
patent: 6359328 (2002-03-01), Dubin
patent: 6441492 (2002-08-01), Cunningham
patent: 6537902 (2003-03-01), Orita
patent: 6605874 (2003-08-01), Leu et al.
patent: 6613664 (2003-09-01), Barth et al.
patent: 6680540 (2004-01-01), Nakano et al.
patent: 6709874 (2004-03-01), Ning
patent: 6878632 (2005-04-01), Nogami et al.
patent: 2001/0030366 (2001-10-01), Nakano et al.
patent: 2001/0055873 (2001-12-01), Watanabe et al.
patent: 2002/0027261 (2002-03-01), Besser et al.
patent: 2002/0079589 (2002-06-01), Gayet et al.
patent: 2003/0148618 (2003-08-01), Parikh
patent: 1022770 (2000-07-01), None
patent: 1022770 (2000-07-01), None
patent: 62-270778 (1987-11-01), None
patent: 11-288940 (2000-07-01), None
patent: PCT/US03/12967 (2003-04-01), None
patent: WO 03/094209 (2003-11-01), None
“Electroless Cu for VLSI”; James S.H. Cho et al.; MRS Bulletin/ Jun. 1993, pp. 31-38.
“Electroless Copper Depostion on Metals and Metal Silicides”; Cecilia Y. Mak; MRS Bulletin/Aug. 1994, pp. 55-62.
“Selective and Blanket Electroless Cu Plating Initiated By Contact Displacement For Deep Submicron Via Contact Filling”; Dubin et al.; VMIC Conf.; Jun. 27-29, 1995, pp. 315-321.
“035 um Cu-Filled Via Holes By Blanket Deposited Electroless Copper On Sputtered Seed Layer”; Yosi Shacham-Diamond et al.; VMIC Conf. ; Jun. 27-29, 1995, pp. 334-336.
“Barriers Against Copper Diffusion into Silicon and Drift Through Silicon Dioxide”; Shi-Qing Wang; MRS Bulletin/Aug. 1994, pp. 30-40.
“Inlaid Copper Multilevel Interconnections Using Planarization by Chemical-Mechanical Polishing”; S.P. Murarka et al.; MRS Bulletin/Jun. 1993, pp. 46-51.
“Electrochemically Deposited Diffusion Barriers”; M. Paunovic; et al. J. Electrochem, Soc., vol. 141, No. 7; Jul. 1994, pp. 1843-1850. © The Electrochemical Society, Inc.
“Electroless Copper Deposition For Multilevel Metallization”; S. Simon Wong et al.; Mat. Res. Soc. Symp. Proc. vol. 203; 1991 Materials Research Society, pp. 347-356.
“Thick Selective Electroless-Plated Cobalt-Nickel Alloy Contacts to CoSi2”; G.E. Georgiou, F. et al. J. Electrochem. Soc., vol. 138, No. 7, Jul. 1991; pp. 2061-2069. © The Electrochemical Society, Inc.
“Encapsulated Copper Interconnection Devices Using Sidewalls Barriers”, Donald S. Gardner et al.; VMIC Conference; Jun. 11-12, 1991, pp. 99-108.
“Planar Copper-Polymide Back End of the Line Interconnections for ULSI Devices”; B. Luther et al. VMIC Conference; Jun. 8-9, 1993, pp. 15-21.
“Electroless plating of copper at a low pH level”, R. Jagannathan et al.: IBM J. Res. Develop. vol. 37. No. 2: Mar. 1993, pp. 117-123.
“Selective Electroless Metal Deposition for Integrated Circuit Fabrication”, Chiu H. Ting et al.; J. Electrochem Soc. vol. 136, No. 2; Feb. 1989, pp. 456-461. The Electrochemical Society, Inc.
“Selective Electroless Metal Deposition for Via Hole Filling in VLSI Multilevel Interconnection Structures”; Chiu H. Ting et al.; J. Electrochem Soc. vol. 136, No. 2; Feb. 1989, pp. 462-465. © The Electrochemical Society, Inc.
“Pd/Si plasma immersion ion implantation for selective elctroless copper plating on SiO2”; Kiang et al.; Applied Phys. Lett. 60 (22): Jun. 1, 1992, pp. 2767-2769. The American Institute of Physics.
“Selective electroless Ni deposition on a TiW underlayer for integrated circuit fabrication”; V.M. Dubin et al.; Thin Solid Films, 226(1993), pp. 87-93.
“Copper Corrosion With and Without Inhibitors”; V. Brusic et al.; J. Electrochem. Soc. vol. 138, No. 8, Aug. 1991, pp. 2253-2259. ©The Electrochemical Society, Inc.
“100 nm wide copper lines made by selective electroless deposition”; Yosi Shacham-Diamand; J. Micromech. Microeng. 1 (1991). pp. 66-732.
“A Half-Micron Pitch Cu Interconnection Technology”; Kazuyoshi Ueno et al.; 1995 Symposium on VLSI Technology Digest of Technical Papers. pp. 27-28.
“Electroless Metal Deposition From Aqueous Solutions”, V.V. Sviridov; Minsk Bielorussion State University; 1987. pp. 60-85.
“Passivation of Copper by Silicide Formation In Dilute Silane”, S. Hymes, et al. Conf. Proc. USLI-VII, Materials Research Society; 1992, pp. 425-431.
“Copper Interconnection with Tungsten Cladding for ULSI”; J.S.H. Cho et al.; ULSI Tech. Symp; 1991; pp. 39-40.
C.J. Sambucetti et al. Electroless Deposition of Thin Alloy Layers for Metal Passivation and Solder Barriers. Aug. 31, 1997, Electromechanical Society Proceedings, vol. 97-27,pp. 336-345, XP001058382.
S.D. Lopatin et al., “Thin Elctroless Barrier for Copper Films”, Proceedings of thje SPIE, SPIE Bellingham, VA, vol. 3508, Sep. 23, 1998, pp. 65-77, XP001058166.
Osaka et al., “Preparation of CoB Soft Magentic Thin Films by Electroless Plating,” IEEE Translation Journal on Magnetics in Japan, vol. 6, No. 1, Jan. 1991, pp. 85-90.
Watanabe et al., “Direct Electroless Nickel Painting on Copper Circuits Using DMAB as a Second Reducing Agent,” 1998 IEMT/IMC Proceedings, pp. 149-153.
Dubin, et al., “Selective Electroless Ni Deposition onto Pd-activated Si for Integrated Circuit Fabrication,” Thin Solid Films, 226, 1993, pp. 94-98.
Palmans, et al., “Deveolpment of an Electroless Copper Deposition Bath for Via Fill Application on TIN Seed Layers,” Conf. Proc. ULSI-X, Materials Research Society, 1995, pp. 87-94.

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