Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-03-31
2001-08-21
Chaudhari, Chandra (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C438S016000, C430S005000
Reexamination Certificate
active
06279147
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to improved semiconductor processing via improved test masks. In particular, the present invention relates to making and using improved lithography/etch/implantation test masks that contain existing product maps.
BACKGROUND ART
Microlithography processes for making miniaturized electronic components, such as in the fabrication of computer chips and integrated circuits, are of increasing importance as the trend towards miniaturization and integration continues. Lithography is one of the key technologies that drives the growth of the integrated circuit industry. Other important semiconductor processes include etch processes and implantation processes. These processes are building tools for fabricating integrated circuit chips.
Lithography processes, etch processes and implantation processes involve the use of masks. Masks contain patterns of translucent/transmissive areas and opaque/blocking areas. Masks function by selectively preventing or blocking a substance, such as light, electron beams, ions, etchants, etc., from portions of a subject substrate while permitting the substance to contact other portions of the subject substrate. In these semiconductor mask processes, improved masks and improved mask processing are desired since they would lead to improved products.
Lithography masks are employed to selectively irradiate a resist covered semiconductor substrate. Etch masks are used to selectively remove exposed areas of an underlying substrate. Ion implantation masks are used to selectively implant ions in exposed areas of an underlying substrate. Such masks are a critical aspect of semiconductor processing and lithographic processing in particular because they play an important role in achieving ever decreasing pattern specifications. Important factors associated with making and using masks include pattern position accuracy, feature size control, and defect density. Masks, whether they are lithography masks or etch masks or ion implantation masks, are made in compliance with a desired design rule (the design rule is derived from numerous aspects of the process).
Prior to using product masks in semiconductor processing (hereinafter termed using a “product mask”), a so-called “test mask” is fabricated to confirm and optimize the operability of a prospective mask design and technology, such as the relationships between patterning, etching, implants, and the like. In other words, test masks permit one to evaluate the technology (such as the acceptability of patterning, etching, and the like) of a prospective mask design. One concern associated with making and using masks, whether the mask is a product mask or a test mask, is that fabrication is complex and costly. Referring to
FIG. 1
, a conventional test mask
10
is shown. A conventional test mask
10
has test patterns
12
over a substrate. The test patterns
12
define various slits or openings
14
in the mask. The test mask
10
is used to determine whether or not the test patterns
12
lead to the production of desired patterned structures (in the case of a lithography test mask).
Another concern regarding masks is that a product mask derived from a corresponding test mask behaves in a different manner. These differences deleteriously impact subsequent semiconductor processing. For example, differences between a product mask and a corresponding test mask may lead to undesirable changes in resist images. During the image-wise irradiation, dense fields may change the amount of light (intensity) passing through the mask. During development, unanticipated concentrations of development components in localized areas affect the size and shape (such as sidewall slope) of openings. This is especially troublesome as resists having a poor slope undesirably permit implants to reach the underlying substrate.
Generally speaking, a lithography product mask that provides a patterned resist which does not accurately reflect the pattern formed by the test mask requires additional engineering and study in order to further refine/compensate the product mask, otherwise the electrical characteristics of semiconductor devices made therewith are unreliable. Such refinement undesirably consumes time and money. It is therefore desirable to provide product masks that act in the same manner as their corresponding test masks.
SUMMARY OF THE INVENTION
The present invention provides an improved semiconductor processing including improved lithographic processing, improved etch processing and improved implantation processing. The present invention specifically provides test masks and methods of making and using test masks useful in lithographic processing, etch processing, implantation processing, and other processing steps. Semiconductor mask processing is improved because the test masks of the present invention behave in substantially the same manner as product masks derived therefrom. As a result, expensive, complex and time consuming efforts to re-engineer product masks that behave differently from their corresponding test masks are minimized and/or eliminated.
One aspect of the present invention relates to a method of making a test mask, involving the steps of providing an existing product mask pattern having a first pattern; removing a portion of the first pattern from the existing product mask; and forming a test pattern in the portion of the existing product mask pattern to provide the test mask, wherein the first pattern of the existing product mask pattern is substantially similar in at least one of pattern density, pattern variability, pattern size, pattern shape, preferential direction, and pattern scribe with the test pattern.
Another aspect of the present invention relates to a method of making a test mask, involving the steps of forming a test pattern in a portion of a mask; and providing an existing product mask pattern having a first pattern in another portion of the mask to provide the test mask, wherein the first pattern of the existing product mask is substantially similar in at least one of pattern density, pattern variability, pattern size, pattern shape, preferential direction, and pattern scribe with the test pattern.
Yet another aspect of the present invention relates to a test mask, containing a wall paper portion comprising a first pattern from an existing product mask pattern; and a test portion comprising a test pattern, wherein the first pattern of the existing product mask pattern is substantially similar in at least one of pattern density, pattern variability, pattern size, pattern shape, preferential direction, and pattern scribe with the test pattern.
Still yet another aspect of the present invention relates to a method of using a test mask involving the steps of providing the test mask comprising a wall paper portion comprising a first pattern from an existing product mask pattern and a test portion comprising a test pattern, wherein the first pattern of the existing product mask pattern is substantially similar in at least one of pattern density, pattern variability, pattern size, pattern shape, preferential direction, and pattern scribe with the test pattern; using the test mask in a semiconductor process with a subject substrate; and evaluating the subject substrate.
REFERENCES:
patent: 5300786 (1994-04-01), Brunner et al.
patent: 5439764 (1995-08-01), Alter et al.
patent: 5681674 (1997-10-01), Fujimoto
patent: 5721074 (1998-02-01), Bae
patent: 5784292 (1998-07-01), Kumar
patent: 5790254 (1998-08-01), Ausschnitt
patent: 5910847 (1999-06-01), Van der Werf et al.
patent: 54-102972 (1979-08-01), None
patent: 62-102528-A (1987-05-01), None
patent: 1145735-A (1989-06-01), None
patent: 5333526-A (1993-12-01), None
IBM Technical Disclosure Bulletin, “Exposure Mask Diagnostic and Dispersion Targets”, Mar. 1980, vol. 22, Issue No. 10, pp. 4505-4507.
Buynoski Matthew S.
Lukanc Todd
Subramanian Ramkumar
Advanced Micro Devices , Inc.
Amin & Turocy LLP
Chaudhari Chandra
Pert Evan
LandOfFree
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