Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-11-08
2004-09-07
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S702000, C438S952000
Reexamination Certificate
active
06787452
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of fabricating integrated circuits and other electronic devices and in particular to an improved method of photoresist patterning that involves a removable anti-reflective coating during the formation of dual damascene structures.
BACKGROUND OF THE INVENTION
Photoresist processing is a key element that must be controlled in order to achieve a low cost, high throughput manufacturing method for the production of integrated circuits in semiconductor devices. Integrated circuits are typically formed by the sequential deposition of layers on a substrate. Each layer is usually patterned by first exposing a photoresist film on a substrate through a mask that contains a device pattern defined by opaque regions consisting of chrome and transparent regions such as quartz. Then the developed pattern in the photoresist film is transferred through an underlying substrate layer by means of a plasma etch process. Alternately, the photoresist pattern can serve as a mask for an ion implant step into an underlying layer. In back end of line (BEOL) processing, patterns consisting of trenches and via holes are filled with a conductive material to form interconnects comprised of horizontal connections or trenches within a layer and vertical connections or via holes between two layers. Conductive materials used in the interconnects are separated by insulating or dielectric materials to prevent crosstalk between the metal wiring. A popular method of manufacturing metal interconnects is a dual damascene structure in which vias and trenches are filled simultaneously with metal in an efficient, high yield process.
A low k dielectric material such as the example described in U.S. Pat. No. 6,287,990 is preferred as an insulation layer. Carbon is incorporated into a silicon dioxide layer to lower the k value. SiO
2
with a dielectric constant (k) of 4 has been widely used in the industry but new technology generations require a low k of about 2.5 or less. The layer in this prior art is deposited by a plasma enhanced chemical vapor deposition (PECVD) technique involving a silane having a Si—C—H moiety and an oxidizing gas such as oxygen or N
2
O.
There is a constant focus on reducing the size of metal interconnects so that devices with higher performance can be provided to satisfy demand. The lithography method used to define patterns is constantly being optimized to enable the printing of features such as lines/spaces, trenches, or contact holes with smaller critical dimensions (CD). A CD is usually a small space width or line width that controls the ultimate performance of the device. For example, finer gate widths allow a faster transistor speed while denser line/space arrays result in more memory storage per unit area. A smaller critical dimension (CD) in a feature such as a trench is more easily printed when the process is optimized to decrease the K constant or when &lgr; is reduced according to the equation, R=K&lgr;/NA. R is the minimum CD that can be resolved while K is a process constant, &lgr; is the exposure wavelength, and NA is the numerical aperture of the exposure tool. In recent years, technology nodes have progressively moved from 250 nm through 180 nm and 130 nm and are now in the 100 nm regime for CD sizes. As a result, the preferred &lgr; which has been 248 nm for CD sizes from about 250 nm through 130 nm is now shifting to 193 nm for features smaller than 130 nm.
The process constant K can be lowered in a variety of ways such as phase shifted masks, improved illumination methods, and optimized photoresist imaging techniques. No matter which wavelength of radiation is used to expose the photoresist, reflectivity control of radiation off the underlying layer is always a concern. Typically, a CD specification includes the requirement that the feature must be maintained within ±10% of a targeted dimension. This includes mask error factors, photoresist line width variations, and an etch transfer component. Therefore, the photoresist contribution to the ±10% allowed variation must be considerably less than 10% in order not to consume the entire budget. One method that has been successfully implemented in many cases is an anti-reflective coating or ARC which is coated prior to the photoresist and greatly minimizes the reflected light from the substrate during the exposure process. The ARC thickness is typically around 1000 Angstroms or less while some photoresist layers have a thickness as thin as 2000 Angstroms. The photoresist pattern must be transferred through the ARC and into an underlying substrate. A thin ARC is preferred since the ARC/photoresist etch rate ratio is close to 1:1 and enough photoresist must remain after the ARC open etch to serve as an etch mask for transferring the pattern into the substrate.
CD variations in the photoresist pattern may result from topography in which the substrate is not level. This leads to thickness variations in the photoresist coating that can be larger than 100 Angstroms. Small changes in photoresist thickness on the order of 100 Angstroms or less are known to result in significant CD variations. Even if the substrate is level, differing compositions within the substrate may cause a CD variation in the photoresist pattern. For example, the photoresist pattern may cross over metal lines contained within the substrate. The metal lines are likely to have a higher reflectivity than the surrounding substrate and thereby cause a higher amount of reflected light which re-exposes the photoresist from below. If the photoresist feature is a line/space array crossing above a metal line, the resulting photoresist line will be smaller in width where it passes over metal than where it crosses over a less reflective part of the substrate. This is true for a positive tone composition in which regions of exposed photoresist are washed away in an aqueous base developer and unexposed areas remain on the substrate. For negative tone photoresists, exposed regions remain on the substrate and unexposed areas are washed away in developer. With a negative tone composition, a photoresist line would become larger with an increased dose from reflected light. In either case, reflectivity control provided by an ARC is crucial for maintaining a line width or CD within a ±10% specification and for achieving a manufacturable process when a highly reflective substrate is involved.
A photoresist process is further characterized by its process latitude which is the range of exposure dose and focus settings that can be applied while still maintaining the CD within a ±10% variation. By controlling reflectivity, an ARC enables a larger process latitude than is realized in the absence of an ARC. Thus, an ARC can prevent a considerable amount of expensive rework caused by a CD being out of specification. Reworking a substrate consists of stripping the patterned film, recoating and re-exposing a new photoresist layer. Rework slows throughput by tying up process and measurement tools for unscheduled period of time.
An important property of an ARC is that its refractive index which is comprised of a real component (n) and an imaginary component (k) can be tuned in many cases by adjusting the composition of the material to minimize reflectivity at the photoresist/ARC interface which improves line width control in the photoresist layer. Another valuable property of an ARC is a high optical absorbance so that light which enters the ARC layer does not reflect off the underlying substrate and re-expose the photoresist layer from below. ARCs are commercially available as organic spin-on coatings that are baked at curing temperatures of about 175° C. to 225° C. to render them immiscible with liquid photoresist solutions that are subsequently spin coated on the ARC. Inorganic ARCs such as SiO
X
N
Y
can be deposited with a PECVD technique at temperatures up to 400° C. Examples of both types are provided in U.S. Pat. No. 6,323,121 in which a silicon oxynitride is formed as an etch stop material and a spin
Hsia Liang Choo
Huang Liu
Sudijono John
Chartered Semiconductor Manufacturing Ltd.
Dang Phuc T.
Pike Rosemary L. S.
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