Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-04-17
2001-04-03
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S648000, C438S647000, C438S651000, C438S655000
Reexamination Certificate
active
06211083
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process used to form Self-ALIgned metal siliCIDE, (SALICIDE), regions on polysilicon, as well as on single crystalline silicon regions.
2. Description of Prior Art
The use of salicide on specific regions of metal oxide semiconductor field effect transistor, (MOSFET), devices, has been used to increase device performance. Salicide, or self-aligned metal silicide layers, such as titanium disilicide or cobalt disilicide, on MOSFET polysilicon gate structures, or word lines, or on MOSFET source/drain regions, decrease the resistance of these elements, thus resulting in the desired increase in MOSFET performance. However the trend to very narrow polysilicon word lines has presented difficulties in obtaining the desired salicide resistance, as well as sometimes resulting in adhesion loss between the salicide regions and the underlying, narrow width, polysilicon gate structure, thus suggesting the need for optimization of the salicide formation process.
A process sequence now being used for salicide formation entails deposition of a metal layer, such as titanium, followed by a first anneal procedure, resulting in a high resistance phase, (C49), of metal silicide, on regions on which the metal overlaid either polysilicon, or single crystalline silicon. After removal of unreacted metal, from the surface of insulator layers, such as spacers on the sides of word line structures, a second anneal is performed to convert the high resistance, metal silicide, to a lower resistance, second phase, or a C54 phase of metal silicide. However the high tensile stress of metal silicide, on narrow width, polysilicon gate structures, or word lines, can result in a greater degree of distortion of the polysilicon word line, or a greater degree of metal silicide peeling from the underlying, narrow width, polysilicon word line, when compared to counterparts comprised of metal silicide overlaying wider width, polysilicon gate structures, or word lines. In addition the exposure of the metal silicide, C49 phase to the ambient used for the second anneal procedure, can result in inclusion of oxygen and nitrogen in the metal silicide layer, not allowing the lower resistance offered by metal silicide, C54 phase to be realized.
This invention will describe a process sequence for formation of salicide layers, on narrow width, polysilicon gate structuresm, or word line, in which a capping layer of silicon oxide, with a compressive stress, is used to alleviate the tensile stress phenomena exhibited by the metal silicide layer, during the second anneal procedure, thus reducing the peeling of metal silicide from narrow width, polysilicon word lines. In addition the use of the capping silicon oxide layer, deposited prior to the second anneal procedure, protects the underlying metal silicide layer from inclusion of resistance increasing oxygen, and nitrogen, present in the anneal ambient. Prior art such as Apte et al, in U.S. Pat. No. 5,593,924, describe a salicide process in which a titanium nitride capping layer is used. However the use of a titanium nitride capping layer, may not neutralize the tensile stress of subsequent metal silicide layers. In addition that prior art uses a first capping layer, overlaying the metal layer prior to formation of a metal silicide layer, with the first capping layer removed prior to the second anneal procedure. That in turn subjects the first phase of the metal silicide layer to the capping layer removal procedure, wherein the present invention, in which the capping layer can remain as part of the final MOSFET structure, does not allow the C49, or the C54 metal silicide phase to be subjected to the capping layer removal procedure, which can degrade the exposed metal silicide layers.
SUMMARY OF THE INVENTION
It is an object of this invention to form a metal silicide layer on a polysilicon gate structure, or word line, and on a source/drain region, of a MOSFET device.
It is another object of this invention to initially form a C49 phase, metal silicide layer, followed by an anneal procedure, used to convert the C49 phase, metal silicide layer, to a lower resistance, C54 phase, metal silicide layer.
It is still another object of this invention to deposit a capping silicon oxide layer, prior to the anneal procedure, used to convert the C49 phase, metal silicide layer, to the C54 phase, metal silicide layer.
In accordance with the present invention, a method of forming a low resistance, metal silicide layer, on a polysilicon gate structure, or word line, as well as on a source/drain region, of a MOSFET device, featuring the use of a silicon oxide, capping layer, formed prior to an anneal cycle, used to convert a high resistance, metal silicide layer, to a lower resistance, metal silicide layer, is described. After formation of a polysilicon gate structure, on an underlying gate insulator layer, a lightly doped source/drain region is formed in an area of a semiconductor substrate, not covered by the polysilicon gate structure. After formation of insulator spacers, on the sides of the polysilicon gate structure, or word line, a heavily doped source/drain region is formed in an area of the semiconductor substrate, not covered by the polysilicon word line structure, or by the insulator spacers. After deposition of a metal layer, a first anneal procedure is used to form a high resistance, metal silicide layer on the top surface of the polysilicon word line structure, and on the surface of the heavily doped source/drain region. After removal of unreacted metal, from the surface of the insulator spacers, a capping, silicon oxide layer is deposited. A second anneal procedure is then performed converting the high resistance, metal silicide layer, underlying the capping, silicon oxide layer, to a lower resistance, metal silicide layer. Deposition of an interlevel dielectric layer, (ILD), overlying the capping, silicon oxide layer, is followed by contact hole openings in the ILD and the capping silicon oxide layer, exposing a portion of the top surface of the low resistance, metal silicide layer, in a region overlying the heavily doped, source/drain region. A metal plug structure is then formed in the contact hole.
REFERENCES:
patent: 4923822 (1990-05-01), Wang et al.
patent: 5384285 (1995-01-01), Sitaram et al.
patent: 5593924 (1997-01-01), Apte et al.
patent: 5960319 (1999-09-01), Iwata et al.
patent: 5970370 (1999-10-01), Besser et al.
patent: 6001721 (1999-12-01), Huang
patent: 6107131 (2000-08-01), Huang
Chung Chaucer
Huang Yuan-Chang
Yang Jiunn-Der
Ackerman Stephen B.
Fahmy Wael
Lee Hsien-Ming
Saile George O.
Taiwan Semiconductor Manufacturing Company
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