Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-05-22
2000-07-04
Chaudhuri, Olik
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438644, 438661, 438674, 438687, H01L 214763
Patent
active
060838299
ABSTRACT:
A method for fabricating a copper interconnect structure, using a low resistivity Cu.sub.3 Ge intermetallic layer, as an adhesive layer, has been developed. Following an in situ, CVD of a titanium nitride barrier layer, a germanium layer, and a copper layer, an anneal procedure is used to form the Cu.sub.3 Ge intermetallic layer, with the intermetallic layer, located between the underlying titanium nitride barrier layer, and the overlying copper layer. The Cu.sub.3 Ge intermetallic layer can also be formed in situ, during deposition, if the deposition temperature exceeds 150.degree. C. Cu.sub.3 Ge layer exhibits a resistivity of about 5E-6 ohm - cm. A second iteration of this invention allows a thick copper layer to be plated on a thin copper seed layer, only on the top surface of a semiconductor substrate. This iteration, also incorporating the low resistivity, Cu.sub.3 Ge intermetallic, and the adhesive layer, prevents copper from being plated on the beveled edge of the semiconductor substrate.
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Chen Lih-Juann
Lai Jane-Bai
Liu Chung-Shi
Yu Chen-Hua Douglas
Ackerman Stephen B.
Chaudhuri Olik
Eaton Kurt
Saile George O.
Taiwan Semiconductor Manufacturing Company
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