USB schedule prefetcher for low power

Details USB schedule prefetcher for low power USB schedule prefetcher for low power

2008-03-04

2008-03-04

Dang, Khanh (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S313000, C713S330000

Reexamination Certificate

active

11004011

ABSTRACT:
A circuit for monitoring future Universal Serial Bus (USB) activities is described. Specifically, the circuit may comprise a Direct Memory Access (DMA) engine schedule prefetcher. The DMA engine schedule prefetcher accesses linked list schedule structures in main memory. The structures are checked for future frames where the linked list has USB activity scheduled. A periodic DMA engine subsequently accesses main memory only during frames where USB traffic is scheduled.

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Definition of Dynamic Random Access Memory from Wikipedia, undated.

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