Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-09-14
2001-01-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S625000, C438S627000, C438S633000, C438S637000, C438S643000, C438S644000
Reexamination Certificate
active
06180506
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to semiconductor integrated circuit devices. More specifically, it relates to damascene conductor lines formed within an integrated circuit. This invention also relates to the method for producing such a damascene conducting line within a semiconductor integrated circuit.
BACKGROUND OF THE INVENTION
Integrated circuits may contain millions of transistors and other circuit elements fabricated on a single semiconductor substrate chip. For an integrated circuit device to be functional, a complex array of signal pads must be routed to connect the circuit elements distributed on the surface of the chip. This routing is done through the use of a wiring network that includes metal interconnect lines formed from a metal conductive film which is deposited onto the surface, then patterned. As complexity and level of integration grow, the efficient routing of signals across an integrated circuit chip becomes increasingly more difficult.
In recent years, to address this need, it has become increasingly popular for an integrated circuit device to contain multiple layers of an interconnect material (i.e., multi-level metallization), each of which can connect the transistors and other circuit elements which comprise an integrated circuit device. After each metallization layer is deposited, a series of metal interconnect lines must be formed from that metallization level. There are a number of techniques which can be used to produce the patterned wiring circuitry needed to connect the transistors and other circuit elements. One method of patterning the interconnect film is to deposit the conductive metal film on top of the device surface, use a photosensitive film to produce a pattern on top of the conductive metal film, then etch away the exposed portions of the film to produce a pattern of the metal film which is wholly on top of the existing structure.
Another, more attractive process used to produce this patterning within a metal interconnect film is the damascene technique. This technique involves first forming a network of channels within the top surface of a preferably planar insulation layer, typically a dielectric film. Then, a conductive film is deposited on top of the etched insulation layer, as well as into the channel, which preferably becomes filled with the conductive material. Subsequent planarization and polishing processes remove the conductive film from the top-most surface of the insulation layer and leave the conducting material in the channels, thereby forming a series of patterned conductive metal lines. This process is described in detail in U.S. Pat. No. 4,944,836 issued to Byer et al. on Jul. 31, 1990.
The damascene technique is particularly attractive because, after the interconnect wires are defined, the resulting upper surface is planar. Step coverage issues need not be addressed during subsequent processing levels for a planar surface. Therefore, the deposition and patterning of subsequent metal films is made much easier. A major limitation in multi-level metallization integrated circuit devices is the issue of step coverage of the multiple metallization layers. When one metallization line traverses a previously produced line of metal or other underlying film, with a conformal dielectric film in between them, undesirable effects result at the point where the upper metal film steps over the patterned lower metal film. The patterning and etching process for the second layer metal can produce defects at the point where the upper level metallization steps over the underlying pattern; the film may be thinner and more subject to attack than the bulk of the metal line in the upper layer.
When multiple layers of metallization are used, this effect is multiplied. Not only are there more steps, and more layers of steps, but steps with more severe heights result at the intersection point where a metal line criss-crosses an underlying metal line. These problems are due, in part, to the substantially planar nature of a coated photoresist film. In the worst case, these intersection points may protrude above the photoresist film. If this occurs, then the exposed film may be subject to attack or destruction during subsequent processing.
In addition to the previous concerns, a subsequently deposited film may not completely cover these extreme steps. With the damascene process, the metal and the dielectric which insulates the metal form one planar surface at each metallization level, and step coverage issues need not be addressed for subsequent processes. This is a significant advantage of the damascene process.
The damascene process is understood to be limited, however, by the difficulty of incorporating a barrier metal, also known as a redundant or shunt layer, within the metallized film. The metal films commonly used to form the interconnect level of semiconductor devices are typically aluminum alloys. Aluminum copper (AlCu), aluminum silicon (AlSi), and aluminum copper silicon (AlCuSi) are some of the more common alloys used in semiconductor processing. Without a barrier layer metal, these aluminum alloy films are subject to voiding due to stress, and failure due to electromigration. These effects are highly undesirable in semiconductor integrated circuit fabrication; they make multi-level metallization devices vulnerable to failure by producing opens at the interface where one level of metal contacts another.
In the semiconductor processing industry, the deposition of the barrier metal is typically done following the complete deposition of the bulk metal or metal alloy film (e.g., AlCu) which forms the conductive part of the interconnect wire. Because the channels are completely filled by this bulk film in the damascene process, however, a redundant layer positioned on top of the bulk film and over the top of the channel is removed when the subsequent planarization and polishing process takes place.
A method of adding a barrier metal to a damascene metal line involves initially polishing the bulk film to a depth lower than that of the top surface of the dielectric film. Then a barrier metal film, typically a refractory metal, is deposited to fill the channel. The barrier metal film must be later polished, however, as was the bulk film. This method requires additional processing steps and material. Therefore, it requires additional expense and is undesirable.
The deficiencies of the current damascene metallization technique show that a need exists for a process to produce a damascene metallization line which contains a barrier metal and does not require additional processing steps. An object of the subject invention is to present a damascene metal line which includes a barrier metal. Another object is to refine and improve the manufacturing process to produce such a line.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention addresses the shortcomings of the damascene processes known to the prior art and provides an improvement to the current damascene technology. The present invention provides a method for forming a damascene metallization line using a bulk metal conductive film and also containing a layer of barrier metal to prevent electromigration failure and stress voiding, without additional processing steps, and therefore without the associated additional expenses.
An upper redundant layer can be formed by depositing either a reactive or non-reactive layer part-way through the deposition of the bulk metal conductive film onto the substrate. The point at which the deposition of the bulk metal film is stopped and when the additional barrier layer is introduced is chosen based on the width of the feature to be filled.
First, an opening such as a trench is created within the top surface of a dielectric film formed on the semiconductor substrate. Then, the aluminum alloy or other bulk metal conductive film is deposited onto the surface. The deposition is stopped when the film partially fills the channels within the dielectric, leaving a “trench-within-a-t
Berry Rene{acute over (e)} R.
International Business Machines - Corporation
Jay H. Anderson, Esq.
Nelms David
Ratner & Prestia
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