Upper-bound calculation for placed circuit design performance

Details Upper-bound calculation for placed circuit design performance Upper-bound calculation for placed circuit design performance

2006-05-23

2006-05-23

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07051312

ABSTRACT:
Within a computer automated tool, a method (400) of estimating an upper-bound of an operational frequency of at least a portion of a placed circuit design can include identifying (405) a clock source within the placed circuit design, wherein the clock source is associated with a clock domain, and determining (410) an initial routing of the clock domain. The method also can include determining (420) a minimum path slack corresponding to each connection of the clock domain. Connections of the clock domain which have a lowest minimum path slack can be marked (430). One or more marked connections which are not routed in delay mode can be identified and routed in delay mode (455) allowing sharing of routing resources by different nets.

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Donath et al. “Timing Driven Placement Using Complete Path Delays”, 27th ACM/IEEE Design Automation Confererence, 1990, pp. 84-89.

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