Updating termination for a bus

Details Updating termination for a bus Updating termination for a bus

2001-02-16

2002-08-20

Wong, Peter (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus expansion or extension

C326S030000

Reexamination Certificate

active

06438636

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to buses for processor based systems, and more particularly to updating termination for a bus.
BACKGROUND
Computer systems include a processor, one or more memory devices, and one or more input-output or I/O devices. The processor, the memory devices, and the I/O devices communicate with each other through a bus in the computer system. A bus is a communication link comprising a set of wires or lines connected between the devices listed above. The bus is shared by the devices as they communicate with one another. A bus may also be a set of lines connected between two functional circuits in a single integrated circuit. The bus generally contains a set of control lines and a set of data lines. The control lines carry signals representing requests and acknowledgments and signals to indicate what type of data is on the data lines. The data lines carry data, complex commands, or addresses. A separate set of lines in the bus may be reserved to carry addresses, and these are called address lines. The devices communicate with each other over the bus according to a protocol that governs which devices may use the bus at any one time. The protocol is a set of rules governing communication over the bus that are implemented and enforced by a device that is appointed a bus master. Generally the processor is the bus master, although there may be more than one bus master. Each bus master initiates and controls requests to use the bus.
Two different schemes exist for organizing communication on a bus. A synchronous bus includes a clock pulse in the control lines and is governed by a protocol based on the clock pulse. An asynchronous bus does not rely on a clock pulse to organize communication. Rather, the asynchronous bus is coordinated by a handshaking protocol under which a sender communicates directly with a receiver to transfer data based on a series of mutual agreements. The sender and the receiver exchange a set of handshaking signals over the control lines before, during, and after each data transfer.
Signals are exchanged between the sender and the receiver over the bus in the following manner. The sender includes a separate driver circuit, typically including a tri-state buffer, connected to each bus line it is to send signals to. Likewise, the receiver has a separate receiver circuit connected to each bus line it is to receive signals from. Typically the receiver circuit is a high impedance buffer circuit such as an inverter. When the sender sends a signal on a particular line it directs the appropriate driver circuit to bring the line to a suitable voltage, either high or low. The receiver detects the signal in the appropriate receiver circuit to complete the communication. A reflection of the signal can take place if an input impedance of the receiver circuit or an output impedance of the driver circuit is different from the characteristic impedance of the line. The discontinuity in the impedance causes the reflection. The signal is reflected back and forth along the line and the reflections must dissipate before a new signal can be sent on the line. This slows the operation of the bus and the computer system.
A conventional method of reducing reflection on a bus line is to damp or dissipate the reflections with a termination in a driver circuit or a receiver circuit connected to the bus line. A termination is a dissipating or damping load, typically a resistive device, which has an impedance that substantially reduces a difference between the input impedance of the receiver circuit or the output impedance of the driver circuit and the characteristic impedance of the line. Two types of termination are used. A source termination comprises an impedance placed in a driver circuit connected to a bus line. A parallel termination comprises impedances placed in a receiver circuit and a driver circuit so that impedances are placed at both ends of a bus line.
In some high speed bus structures the implementation of termination techniques to reduce reflection interferes with the quality and speed of signal transfer. There remains a need for a termination of lines in high speed bus structures that does not impair the quality and speed of signal transfer. For these and other reasons there is a need for the present invention.
SUMMARY OF THE INVENTION
According to one embodiment of the present invention, a signal on a line is damped, an edge in the signal is detected and the damping is modified after the edge is detected and before a subsequent edge in the signal is detected. Advantages of the invention will be apparent to one skilled in the art upon an examination of the detailed description of the preferred embodiments.


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