Unrolling hardware design generate statements in a source...

Details Unrolling hardware design generate statements in a source... Unrolling hardware design generate statements in a source...

2006-09-15

2010-10-26

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07823097

ABSTRACT:
Unrolling the “generate” statement of a hardware description language (“HDL”) and displaying the unrolled HDL. For a conditional generate the condition is evaluated. If the statement is true the enclosed HDL code will be displayed. For an iterative generate, the enclosing HDL will be displayed as many times as specified by the bounds of the iteration scheme. This allows, for example, simulation value annotations for signals declared inside the generate statement, semantic navigation inside the generate statements, and allows the user to visualize what is included in the target design.

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Yu-Chin Hsu, Bassam Tabbarra, Yirng-An Chen, Furshing Tsai, Advanced techniques for RTL Debugging, DAC 2003, Jun. 2-6, 2003.

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