Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2011-05-10
2011-05-10
Lugo, David B (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S355000
Reexamination Certificate
active
07940878
ABSTRACT:
A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state.
REFERENCES:
patent: 5475877 (1995-12-01), Adachi
patent: 7420361 (2008-09-01), Lin et al.
patent: 7426018 (2008-09-01), Wassink
patent: 2005/0069071 (2005-03-01), Kim et al.
Baumgartner Steven J.
Buchholtz Timothy C.
Davies Andrew D.
Liang Thomas W.
Maki Andrew B.
Bockhop & Associates LLC
International Business Machines - Corporation
Lugo David B
LandOfFree
Unlock mode in source synchronous receivers does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Unlock mode in source synchronous receivers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Unlock mode in source synchronous receivers will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2664621