Unlock mode in source synchronous receivers

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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Details

C375S355000

Reexamination Certificate

active

07940878

ABSTRACT:
A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state.

REFERENCES:
patent: 5475877 (1995-12-01), Adachi
patent: 7420361 (2008-09-01), Lin et al.
patent: 7426018 (2008-09-01), Wassink
patent: 2005/0069071 (2005-03-01), Kim et al.

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