Unlanded via structure and method for making same

Details Unlanded via structure and method for making same Unlanded via structure and method for making same

1997-11-25

1999-03-09

Powell, William

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

438624, 438639, 438978, 438694, H01L 21302

Patent

active

058800301

ABSTRACT:
A high density, low capacitance, interconnect structure for microelectronic devices has unlanded vias formed with organic polymer intralayer dielectric material having substantially vertical sidewalls. A method of producing unlanded vias includes forming a planarized organic polymer intra-layer dielectric between conductors, forming an inorganic dielectric over the conductor and organic polymer layer, patterning a photoresist layer such that openings in the photoresist layer overlap portions of both the conductor and the intra-layer dielectric, etching the inorganic dielectric and then concurrently stripping the photoresist and anisotropically etching the organic polymer intra-layer dielectric. A second conductor is typically deposited into the via opening so as to form an electrical connection to the first conductor. A silicon based insulator containing an organic polymer can alternatively be used to form the intra-layer dielectric.

REFERENCES:
patent: 4560436 (1985-12-01), Bukham et al.
patent: 4832788 (1989-05-01), Nemiroff
patent: 5451543 (1995-09-01), Woo et al.
patent: 5702981 (1997-12-01), Maniar et al.
patent: 5721157 (1998-02-01), Sunada
patent: 5795820 (1998-08-01), Kepler
"Process Margin Analysis of 0.25mum CMOS Unlanded Vias"; Yew et al., abstract only, 1996 Proceedings Thirteenth International VLSI Multilevel Interconnection Conference (VMIC), 1996.

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