Unlanded via process

Details Unlanded via process Unlanded via process

1999-05-17

2000-12-19

Thomas, Tom

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438624, 438626, 438666, 438675, 438738, 438740, 438742, 438743, 438744, 257773, 257774, H01L 214763, H01L 21302, H01L 2131, H01L 2144, H01L 2940

Patent

active

061627224

ABSTRACT:
A method is provided for forming an unlanded via hole that substantially solves both the problems of high resistance and via profile loss due to etching. A patterned conductor layer on a first dielectric layer is provided firstly. A first insulating layer is then formed on the first dielectric layer and the conductor layer. A second dielectric layer is formed on the first insulating layer and subsequently etched back until the conductor layer is exposed. The following procedure is to form a second insulating layer on the second dielectric layer and the conductor layer. A third dielectric layer is formed on the second insulating layer. Thereafter, a patterned photoresist layer is formed on the third dielectric layer. Then the etching process is used to etch the third dielectric layer and the second insulating layer to form an unlanded via hole. Finally, the photoresist layer is removed. The unlanded via hole proposed in according with the present invention produces an unlanded via having a good profile.

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