Unlanded process in semiconductor manufacture

Details Unlanded process in semiconductor manufacture Unlanded process in semiconductor manufacture

2001-01-23

2003-06-10

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

C438S401000, C438S462000

Reexamination Certificate

active

06576486

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90101007, filed Jan. 17, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating interconnects for interconnecting semiconductor devices. More particularly, the present invention relates to an unlanded process for fabricating interconnects in an integrated circuit.
2. Description of Related Art
In the fabrication of semiconductors, semiconductor devices are connected by a multiple of interconnect layers. Inter-layer connections of various conductive layers are achieved by vias or contacts. To increase alignment margin between conductive lines and via/contact, a landed process or an unlanded process is used. In the landed process, area where the conductive line meets the via/contact is enlarged and distance between conductive lines is increased. Hence, the wider portion of a wider conductive line is prevented from getting too close to another conductive line. In the unlanded process, alignment between the conductive line and the via/contact is increased without increasing distance of separation between neighboring conductive lines. However, as the level of integration for electronic devices continues to increase, landed process of fabricating integrated circuit is gradually replaced by unlanded process.
Conventional unlanded process employs an optical proximity correction (OPC) mask to form conductive lines that connects electrically with via/contact. In general, serif or hammerhead pattern is inserted in a junction region between a conductive line and a via/contact so that alignment margin of the two is increased. Although the addition of serif or hammerhead pattern has definite benefit, alignment accuracy is not high enough to result in substantial improvement in the quality of electrical connection between a conductive line and via/contact.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide an unlanded process for manufacturing semiconductor circuits. An optical proximity correction of a electrical connection region of a conductive line is carried out to increase alignment accuracy between the conductive line and a via/contact. Optical proximity correction of a photomask for forming a conductive line pattern is carried out by first determining the electrical connection regions in the conductive line pattern. The regions are expanded equi-directionally or extended outward direction along the edges of the conductive line to form magnified regions. Overlapping regions between the original conductive line pattern and the magnified regions, regions outside the conductive line pattern as well as regions too close to neighboring conductive line pattern are removed. The final magnified regions and the original conductive line pattern are combined. Ultimately, an optical proximity corrected photomask for forming an accurate conductive line pattern is obtained.
In this invention, areas in the conductive line pattern where electrical connections are formed are magnified. Furthermore, areas in the magnified regions that are too close to neighboring conductive line pattern are deleted to prevent the wider section (due to magnification) of the conductive line getting too close to a neighboring conductive layer. Consequently, the unlanded process is able to increase alignment accuracy between the conductive line and via/contact without a corresponding increase in the distance of separation between neighboring conductive lines.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5610831 (1997-03-01), Matsumoto
patent: 5879844 (1999-03-01), Yamamoto et al.
patent: 6305000 (2001-10-01), Phan et al.
patent: 6365504 (2002-04-01), Chien et al.
patent: 2002/0028523 (2002-03-01), Toyama et al.

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